EPCQL1024F24IN Datasheet EPCQL1024F24IN, EPCQL512F24IN, EPCQL256F24IN | P16-P18

Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 0

Table 19. Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 0

Status Register Content Memory Content

TB Bit BP3 Bit BP2 Bit BP1 Bit BP0 Bit Protected Area Unprotected Area

0 0 0 0 0 None All sectors

0 0 0 0 1 Sector 2047 Sectors (0 to 2046)

0 0 0 1 0 Sectors (2046 to 2047) Sectors (0 to 2045)

0 0 0 1 1 Sectors (2044 to 2047) Sectors (0 to 2043)

0 0 1 0 0 Sectors (2040 to 2047) Sectors (0 to 2039)

0 0 1 0 1 Sectors (2032 to 2047) Sectors (0 to 2031)

0 0 1 1 0 Sectors (2016 to 2047) Sectors (0 to 2015)

0 0 1 1 1 Sectors (1984 to 2047) Sectors (0 to 1983)

0 1 0 0 0 Sectors (1920 to 2047) Sectors (0 to 1919)

0 1 0 0 1 Sectors (1792 to 2047) Sectors (0 to 1791)

0 1 0 1 0 Sectors (1536 to 2047) Sectors (0 to 1535)

0 1 0 1 1 Sectors (1024 to 2047) Sectors (0 to 1023)

0 1 1 0 0 All sectors None

0 1 1 0 1 All sectors None

0 1 1 1 0 All sectors None

0 1 1 1 1 All sectors None

Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 1

Table 20. Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 1

Status Register Content Memory Content

TB Bit BP3 Bit BP2 Bit BP1 Bit BP0 Bit Protected Area Unprotected Area

1 0 0 0 0 None All sectors

1 0 0 0 1 Sector 0 Sectors (1 to 2047)

1 0 0 1 0 Sectors (0 to 1) Sectors (2 to 2047)

1 0 0 1 1 Sectors (0 to 3) Sectors (4 to 2047)

1 0 1 0 0 Sectors (0 to 7) Sectors (8 to 2047)

1 0 1 0 1 Sectors (0 to 15) Sectors (16 to 2047)

1 0 1 1 0 Sectors (0 to 31) Sectors (32 to 2047)

1 0 1 1 1 Sectors (0 to 63) Sectors (64 to 2047)

1 1 0 0 0 Sectors (0 to 127) Sectors (128 to 2047)

1 1 0 0 1 Sectors (0 to 255) Sectors (256 to 2047)

1 1 0 1 0 Sectors (0 to 511) Sectors (512 to 2047)

1 1 0 1 1 Sectors (0 to 1023) Sectors (1024 to 2047)

continued...

EPCQ-L Serial Configuration Devices Datasheet

CF52013 | 2018.05.18

EPCQ-L Serial Configuration Devices Datasheet

Status Register Content Memory Content

TB Bit BP3 Bit BP2 Bit BP1 Bit BP0 Bit Protected Area Unprotected Area

1 1 1 0 0 All sectors None

1 1 1 0 1 All sectors None

1 1 1 1 0 All sectors None

1 1 1 1 1 All sectors None

Write Status Register Operation (01h)

The write status register operation does not affect the write enable latch and write in

progress bits. You can use the write status register operation to set the status register

block protection and top or bottom bits. Therefore, you can implement this operation

to protect certain memory sectors. Refer to Table 15 on page 13 through Table 20 on

page 16. After setting the block protect bits, the protected memory sectors are

treated as read-only memory. You must execute the write enable operation before the

write status operation.

When the operation is in progress, the write or erase controller bit of the flag status

polled

(13)

, with nCS toggled twice in between commands. When the operation

completes, the write or erase controller bit is cleared to 1. The end of operation can be

detected when the flag status register outputs the write or erase controller bit to 1

each time it is polled.

The following figure shows the timing diagram for the write status register operation.

Figure 3. Write Status Register Operation Timing Diagram

Operation Code (01h) Status Register

DATA0

nCS

DCLK

DATA

High Impedance

8 9 10 11 12 13 14 15

01234567

MSB

Immediately after the nCS signal drives high, the device initiates the self-timed write

status cycle. The self-timed write status cycle usually takes 5 ms for all EPCQ-L

devices and is guaranteed to be less than 8 ms. For details about t

, refer to Table

26 on page 30. You must account for this delay to ensure that the status register is

written with the desired block protect bits. Alternatively, you can check the write in

progress bit in the status register by executing the read status register operation while

the self-timed write status cycle is in progress. The flash controller sets the write in

progress bit to 1 during the self-timed write status cycle and 0 when it is complete.

(13)

Poll the flag status register once for EPCQL256, twice for EPCQL512 or four times for

EPQL1024.

EPCQ-L Serial Configuration Devices Datasheet

CF52013 | 2018.05.18

EPCQ-L Serial Configuration Devices Datasheet

Flag Status Register

Table 21. Flag Status Register Bits

Bit Name Value Description

7 Write or Erase

Controller

(14)

• 1=Ready

• 0=Busy

Indicates whether one of the following operation is in

progress:

• Write Status Register

• Write NVCR

• Write Bytes

• Erase

6 Erase suspend • 1=In effect

• 0=Not in effect

Indicates whether an Erase operation has been or is going

to be suspended.

Note: Status bits are reset automatically

5 Erase • 1=Failure or protection

error

• 0=Clear

Indicates whether an Erase operation has succeeded or

failed.

4 Write • 1=Failure or protection

error

• 0=Clear

Indicates whether a Write Bytes operation has succeeded or

failed; also an attempt to write a 0 to a 1 when VPP = VPPH

and the data pattern is a multiple of 64 bits.

3 Reserved

2 Write suspend • 1=In effect

• 0=Not in effect

Indicates whether a Write Bytes operation has been or will

be suspended.

1 Protection • 1=Failure or protection

error

• 0=Clear

Indicates whether an Erase or Write Bytes operation has

attempted to modify the protected array sector.

0 Addressing • 1=4-bytes addressing

• 0=3-bytes addressing

Indicates the addressing mode used.

Read Flag Status Register Operation(70h)

The Read flag status register can be read continuously and at any time, including

during a write or erase operation. You must read the Read flag status register every

time a write or erase command is issued.

Figure 4. Read Flag Status Register Operation Timing Diagram

nCS

DCLK

DATA0

DATA

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

7 6 5 4 3 2 1 0 7 2 1 0 76 5 4 3

Operation Code (70h)

MSB MSB

Status Register Out Status Register Out

High Impedance

(14)

Write or erase controller bit = NOT write in progress bit.

EPCQ-L Serial Configuration Devices Datasheet

CF52013 | 2018.05.18

EPCQ-L Serial Configuration Devices Datasheet

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EPCQL1024F24IN

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FPGA - Configuration Memory

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EPCQL1024F24IN

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