MAX6917
I
2
C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
______________________________________________________________________________________ 11
Detailed Description
Functional Description
The MAX6917 contains eight 8-bit timekeeping registers,
seven 8-bit alarm threshold registers, one status register,
one control register, one alarm-configuration register, and
96 x 8 bits of SRAM. In addition to single-byte reads and
writes to registers and RAM, there is a burst timekeeping
register read/write command, a burst RAM read/write
command, and a battery-test command that allows soft-
ware-commanded testing of the backup battery at any
time. An I
2
C-bus-compatible interface allows serial com-
munication with a µP. When V
CC
is less than the reset
threshold, the serial interface is disabled to prevent erro-
neous data from being written to the MAX6917. A µP
supervisory section and an NVRAM controller are provid-
ed for ease of implementation with µP-based systems. A
crystal fail-detect circuit and a data-valid bit can be used
to guarantee RAM data integrity and valid timekeeping
data. Two reference frequencies outputs, 32.768kHz and
1Hz, are provided for external device clocking. Time and
calendar data are stored in a binary-coded decimal
(BCD) format. Figure 1 shows the functional diagram of
the MAX6917.
Real-Time Clock
The RTC provides seconds, minutes, hours, day, date,
month, and year information. The end of the months is
automatically adjusted for months with fewer than 31
days, including corrections for leap years through 2099.
Crystal Oscillator
The MAX6917 uses an external, standard 6pF load
watch crystal. No other external components are
required for this timekeeping oscillator. Power-up oscil-
lator start time is dependent mainly upon applied V
CC
and ambient temperature. The MAX6917, because of
its low timekeeping current, exhibits a typical startup
time of 1s to 2s.
I
2
C-Compatible Interface
The I
2
C bus allows bidirectional, 2-wire communication
between different ICs. The two lines are serial data line
(SDA) and serial clock line (SCL). Both lines must be
connected to a positive supply through individual
pullup resistors (see the Typical Application Circuit).
Data transfer can only be initiated when the bus is not
busy (both SDA and SCL are high). Figure 2 shows a
timing diagram for I
2
C communication.
Pin Description (continued)
PIN NAME FUNCTION
11 32KHZ 32.768kHz Output. Buffered push-pull output that is enabled from the FOUT configuration register.
12 1HZ 1Hz Output. Buffered push-pull output that is enabled from the FOUT configuration register.
13 SDA Open-Drain Data Input/Output. I
2
C bus serial data input/output connection.
14 SCL Serial Clock Input. I
2
C bus clock for input/output data transfers.
15 ALM
Open-Drain, Active-Low Alarm Output. ALM goes low when RTC time matches alarm thresholds set in
the alarm threshold registers. ALM stays low until cleared by reading or writing to the alarm configuration
register or to any of the alarm threshold registers.
16
Open-Drain, Battery-Low Indicator. BATT_LO is active low when the V
BATT
input is tested below V
BTP
if
the internal trip is selected in the control register (POR default). If external trip is selected in the control
register, then BATT_LO is active low when TRIP is less than V
TRIP
.
18 RESET
Open-Drain, Active-Low Reset Output. RESET pulses low for t
RP
when triggered, and stays low
whenever V
CC
is below the reset threshold or when MR is logic low. RESET remains low for t
RP
after
either V
CC
rises above the reset threshold or MR goes from low to high.
19 V
CC
Main Supply Input. Connect a 0.1µF bypass capacitor from V
CC
to GND.
20 V
BATT
Backup-Battery Input. When V
CC
falls below the reset threshold and V
BATT
, V
OUT
switches from V
CC
to
V
BATT
. When V
CC
rises above V
BATT
or the reset threshold, V
OUT
reconnects to V
CC
. V
BATT
may exceed
V
CC
. Connect V
BATT
to GND if no backup-battery supply is used. Connect a 0.1µF low-leakage bypass
capacitor from V
BATT
to GND.
