MAX6917
I
2
C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
14 ______________________________________________________________________________________
Address/Command Byte
The second byte of data sent after the START condition
is the address/command byte (Figure 8). Each data
transfer is initiated by an address/command byte. Bits
7–1 specify the designated register or RAM location to
be read or written to, and the LSB (bit 0) specifies a
write operation if logic zero or a read operation if logic
one. The command byte is always input starting with
the MSB (bit 7).
Reading from the Timekeeping Registers
The timekeeping registers (seconds, minutes, hours,
date, month, day, and year) and the control register
can be read either with a single read or a burst read
(Figure 9). Since the RTC runs continuously and a read
takes a finite amount of time, there is the possibility that
the clock counters could change during a read opera-
tion, thereby reporting inaccurate timekeeping data. In
the MAX6917, each clock counter’s data is buffered by
a latch. Clock counter data is latched by the I
2
C bus
read command (on the falling edge of SCL when the
slave acknowledge bit is sent, after the address/com-
mand byte has been sent by the master to read a time-
keeping register). Collision-detection circuitry ensures
that this does not happen coincident with a seconds
counter update to ensure accurate time data is being
read. This avoids time-data changes during a read
operation. The clock counters continue to count and
keep accurate time during the read operation.
If single reads are used to read each of the timekeep-
ing registers individually, then it is necessary to do
some error checking on the receiving end. An error can
occur when the seconds counter increments before all
the other registers are read out. For example, suppose
a carry of 13:59:59 to 14:00:00 occurs during single-
read operations of the timekeeping registers. Then the
net data could become 14:59:59, which is erroneous
real-time data. To prevent this with single-read opera-
tions, read the seconds register first (initial seconds)
and store this value for future comparison. When the
remaining timekeeping registers have been read out,
read the seconds register again (final seconds). If the
initial seconds value is 59, check that the final-seconds
value is still 59; if not, repeat the entire single-read
process for the timekeeping registers. A comparison of
the initial-seconds value with the final-seconds value
can indicate if there was a bus-delay problem in read-
ing the timekeeping data (difference should always be
1s or less). Using a 100kHz bus speed, and sequential
single reads, it would take under 2.5ms to read all
seven of the timekeeping registers plus a second read
of the seconds register.
The most accurate way to read the timekeeping regis-
ters is to perform a burst read. With burst reads, the
main timekeeping registers (seconds, minutes, hours,
date, month, day, year) and the control register are
read sequentially, in the order listed with the seconds
register first. They must be all read out as a group of
