MAX6917
I
2
C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
16 ______________________________________________________________________________________
current time by an incomplete write operation, the cur-
rent time value is buffered from being written directly to
the clock counters. The new data sent replaces the cur-
rent contents of this input buffer. This time update data
is loaded into the clock counters after the stop bit at the
end of the I
2
C bus write operation. Collision-detection
circuitry ensures that this does not happen coincident
with a seconds-counter update to guarantee that accu-
rate time data is being written. This avoids time data
changes during a write operation. An incomplete write
operation aborts the time-update procedures and the
contents of the input buffer are discarded. The clock
counters reflect the new time data beginning with the
first 1s clock cycle after the stop bit. The clock counter
is reset immediately after a write to the seconds regis-
ter or a burst write to the timekeeping registers. This
ensures that 1s clock tick is synchronous to timekeep-
ing writes.
If single-write operations (Figure 9) are used to write to
each of the timekeeping registers, then error checking is
needed. If the seconds register is the one to be updat-
ed, update it first and then read it back and store its
value as the initial seconds. Update the remaining time-
keeping registers and then read the seconds register
again (final seconds). If initial seconds was 59, ensure it
is still 59. If initial seconds was not 59, ensure that final
seconds is within 1s of initial seconds. If the seconds
register is not to be written to, then read the seconds
register first and save it as initial seconds. Write to the
required timekeeping registers and then read the sec-
onds register again (final seconds). If initial seconds
was 59, ensure it is still 59. If initial seconds was not 59,
ensure that final seconds is within 1s of initial seconds.
Although both single writes and burst writes are possi-
ble, the most accurate way to write to the timekeeping
counters is to do a burst write (Figure 9). In the burst
write, the main timekeeping registers (seconds, min-
utes, hours, date, month, day, year) and the control
register are written sequentially. They must be all writ-
ten to as a group of eight registers, with 8 bytes each,
for proper execution of the burst-write function. All
seven timekeeping registers and the control register
are simultaneously loaded into the input buffer at the
end of the 2-wire bus write operation. The worst-case
error that can occur between the actual time and the
write time update is 1s.
To avoid rollover issues when writing time data to the
MAX6917, the remaining time and date registers must
be written within 1s of updating the seconds register
when using single writes. For burst writes, all eight reg-
isters must be written within this period (1s).
The weekday data in the day register increments at
midnight. Values that correspond to the day of the
week are user defined, but must be sequential (i.e., if 1
equals Sunday, then 2 equals Monday, and so on). If
invalid values are written to the timekeeping registers,
the operation becomes undefined.
Timeout Feature
The purpose of the bus timeout feature is to reset the seri-
al bus interface and change the SDA line of the MAX6917
from an output to an input, which puts the SDA line into a
high-impedance state. This is necessary when the
MAX6917 is transmitting data and becomes stuck at a
logic-low level. If the SDA line is stuck low, any other
device on the bus is not able to communicate.
The timeout feature looks for a valid START and STOP
condition to determine whether SDA has been stuck
low. A valid START condition initiates the timeout
counter in reference to the internal 1Hz clock. Counting
begins on the first rising edge of the 1Hz clock after a
valid START condition. If a valid STOP condition is
detected before the next rising edge of the 1Hz clock,
the timeout counter is stopped and awaits a new valid
START condition. If a valid STOP condition is not
detected before the next rising edge of the 1Hz clock,
the I
2
C interface resets to the idle state and waits for a
new I
2
C transaction. Depending on the occurrence of
the START condition, that initiates the timeout counter,
in reference to the internal 1Hz clock, the timeout peri-
od can be 1s to 2s. The lower limit of the timeout period
(1s) imposes a limit on the SCL frequency of the
MAX6917 because a burst read/write requires up to 96
bytes of information to be transmitted in between a
START and STOP condition.
