MAX6917
I
2
C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
28 ______________________________________________________________________________________
Freshness-Seal Mode
When the battery is first attached to the MAX6917 without
V
CC
power applied, the device does not immediately pro-
vide battery-backup power to V
OUT
(Figure 19). Only
after V
CC
exceeds V
RST
and later falls below both V
RST
and V
BATT
does the MAX6917 leave freshness-seal mode
and provide battery-backup power. This mode allows a
battery to be attached during manufacturing but not used
until after the system has been activated for the first time.
As a result, no battery energy is drained during storage
and shipping.
Battery-Test Control Register and Other Test Options
There are two warning formats for the BATT_LO and
BATT_ON outputs. By setting D0 (BATT ON BLINK)
and/or D1 (BATT LO BLINK) in the control register to one,
the respective warning output toggles on every 0.5s and
off every 0.5s when set to active low by the internal
MAX6917 logic. This allows a more noticeable warning
indicator in systems where an LED is connected as a sta-
tus or warning light for the end user. The POR default set-
tings of zero leave these outputs set to logic low when
they are active.
D5 (INT/EXT TEST) selects whether the battery-test cir-
cuit is configured as internal or external (Table 1). If D5
is set to zero (default value), then the internal resistor-
divider is used between V
BATT
and GND to select the
battery-low trip point (Figure 17). The internal resistors,
R
SET+_INT
and R
SET-_IINT
, are used to divide V
BATT
in
half, as well as to provide the battery-test-load resis-
tance of 0.91MΩ (typ).
If D5 (INT/EXT TEST) is set to one, then the two external
resistors, R
SET+_EXT
and R
SET-_EXT
, are used to divide
V
BATT
down to the ratio for a trip point set at TRIP of
1.24V (V
TRIP
) (typ). R
SET+_EXT
plus R
SET-_EXT
in series
provide the load resistance used during the 1s every-
24hr-battery test. If additional load resistance is
desired, then an external load resistor, R
LOAD_EXT
, can
be placed between V
BATT
and the collector or drain of
the transistor driven by TEST. The equivalent load resis-
tance used to test the battery is then R
LOAD_EXT
in par-
allel with the series combination of R
SET+_EXT
plus
R
SET-_EXT
. In this mode, the internal resistors are
removed from TRIP and are not used as a load during
the battery-test pulse. TEST pulses high to perform the
battery test and remains low between tests.
One final battery-test feature of the MAX6917 is the
software write address/command of 1Ah that forces a
1s battery test to be performed every time it is sent.
Frequency Outputs
The 1Hz and 32kHz (32.768kHz) frequency outputs
provide buffered, push-pull outputs for timing or clock-
ing of external devices. Each push-pull output is refer-
enced to GND for logic-low output levels and
referenced to V
OUT
for logic-high output levels.
Disabled frequency outputs are held at a logic-low
level. The FOUT configuration register (Table 1) con-
tains individual enable bits that control the state of the
respective frequency output for V
CC
operating mode
and for V
BATT
operating mode.
Bits D5 (32kHz VBATT EN) and D4 (1Hz VBATT EN) in
the FOUT configuration register enable the respective
frequency output when operating from V
BATT
, if set to
one, or disable the respective frequency output if set to
zero. POR settings disable all frequency outputs when
operating from V
BATT
.
