89H64H16AG2ZCBLGI Datasheet 89H64H16AG2ZCBLGI, 89H64H16AG2ZCBL, 89H64H16AG2ZCBLI | P16-P18

16 of 62 November 28, 2011

IDT 89HPES64H16AG2 Data Sheet

PERSTN I Global Reset. Assertion of this signal resets all logic inside

PES64H16AG2.

RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental

reset, PES64H16AG2 executes the reset procedure and remains in a reset

state with the Master and Slave SMBuses active. This allows software to

read and write registers internal to the device before normal device opera-

tion begins. The device exits the reset state when the RSTHALT bit is

cleared in the SWCTL register by an SMBus master.

SWMODE[3:0] I Switch Mode. These configuration pins determine the PES64H16AG2

switch operating mode. Note: These pins should be static and not change

following the negation of PERSTN.

0x0 - Single partition

0x1 - Single partition with Serial EEPROM initialization

0x2 through 0x7 - Reserved

0x8 - Single partition with port 0 selected as the upstream port (port 2 dis-

abled)

0x9 - Single partition with port 2 selected as the upstream port (port 0 dis-

abled)

0xA - Single partition with Serial EEPROM initialization and port 0 selected

as the upstream port (port 2 disabled)

0xB - Single partition with Serial EEPROM initialization and port 2 selected

as the upstream port (port 0 disabled)

0xC - Multi-partition

0xD - Multi-partition with Serial EEPROM initialization

0xE - Reserved

0xF - Reserved

Signal Type Name/Description

JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data

into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is

independent of the system clock with a nominal 50% duty cycle.

JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or

JTAG Controller.

JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary

scan logic or JTAG Controller. When no data is being shifted out, this signal

is tri-stated.

JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the

boundary scan logic or JTAG Controller.

JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary

scan logic and JTAG TAP Controller. An external pull-up on the board is

recommended to meet the JTAG specification in cases where the tester

can access this signal. However, for systems running in functional mode,

one of the following should occur:

1) actively drive this signal low with control logic

2) statically drive this signal low with an external pull-down on the board

Table 7 Test Pins

Signal Type Name/Description

Table 6 System Pins (Part 2 of 2)

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IDT 89HPES64H16AG2 Data Sheet

Signal Type Name/Description

REFRES00 I/O Port 0 External Reference Resistor. Provides a reference for the Port 0

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-

tor should be connected from this pin to ground.

REFRES01 I/O Port 1 External Reference Resistor. Provides a reference for the Port 1

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-

tor should be connected from this pin to ground.

REFRES02 I/O Port 2 External Reference Resistor. Provides a reference for the Port 2

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-

tor should be connected from this pin to ground.

REFRES03 I/O Port 3 External Reference Resistor. Provides a reference for the Port 3

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-

tor should be connected from this pin to ground.

REFRES04 I/O Port 4 External Reference Resistor. Provides a reference for the Port 4

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-

tor should be connected from this pin to ground.

REFRES05 I/O Port 5 External Reference Resistor. Provides a reference for the Port 5

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-

tor should be connected from this pin to ground.

REFRES06 I/O Port 6 External Reference Resistor. Provides a reference for the Port 6

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-

tor should be connected from this pin to ground.

REFRES07 I/O Port 7 External Reference Resistor. Provides a reference for the Port 7

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-

tor should be connected from this pin to ground.

REFRES08 I/O Port 8 External Reference Resistor. Provides a reference for the Port 8

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-

tor should be connected from this pin to ground.

REFRES09 I/O Port 9 External Reference Resistor. Provides a reference for the Port 9

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-

tor should be connected from this pin to ground.

REFRES10 I/O Port 10 External Reference Resistor. Provides a reference for the Port 10

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-

tor should be connected from this pin to ground.

REFRES11 I/O Port 11 External Reference Resistor. Provides a reference for the Port 11

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-

tor should be connected from this pin to ground.

REFRES12 I/O Port 12 External Reference Resistor. Provides a reference for the Port 12

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-

tor should be connected from this pin to ground.

REFRES13 I/O Port 13 External Reference Resistor. Provides a reference for the Port 13

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-

tor should be connected from this pin to ground.

REFRES14 I/O Port 14 External Reference Resistor. Provides a reference for the Port 14

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-

tor should be connected from this pin to ground.

Table 8 Power, Ground, and SerDes Resistor Pins (Part 1 of 2)

18 of 62 November 28, 2011

IDT 89HPES64H16AG2 Data Sheet

REFRES15 I/O Port 15 External Reference Resistor. Provides a reference for the Port 15

SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-

tor should be connected from this pin to ground.

REFRESPLL I/O PLL External Reference Resistor. Provides a reference for the PLL bias

currents and PLL calibration circuitry. A 3K Ohm +/- 1% resistor should be

connected from this pin to ground.

CORE I Core V

DD.

Power supply for core logic (1.0V).

I/O I I/O V

DD.

LVTTL I/O buffer power supply (2.5V or preferred 3.3V).

PEA I PCI Express Analog Power. Serdes analog power supply (1.0V).

PEHA I PCI Express Analog High Power. Serdes analog power supply (2.5V).

PETA I PCI Express Transmitter Analog Voltage. Serdes transmitter analog

power supply (1.0V).

I Ground.

Signal Type Name/Description

Table 8 Power, Ground, and SerDes Resistor Pins (Part 2 of 2)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57 P58-P60 P61-P62

89H64H16AG2ZCBLGI

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PCI Interface IC PCIE GEN2 SWITCH

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