5 of 62 November 28, 2011
IDT 89HPES64H16AG2 Data Sheet
Hot-Plug Interface
The PES64H16AG2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the
PES64H16AG2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset
and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES64H16AG2 generates an SMBus transaction to the I/O
expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on
the IOEXPINTN input pin (alternate function of GPIO) of the PES64H16AG2. In response to an I/O expander interrupt, the PES64H16AG2 generates
an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES64H16AG2 provides 54 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO
pin may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These
alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
Pin Description
The following tables list the functions of the pins provided on the PES64H16AG2. Some of the functions listed may be multiplexed onto the same
pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero
(low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal Type Name/Description
PE00RP[3:0]
PE00RN[3:0]
I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0.
PE00TP[3:0]
PE00TN[3:0]
O PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 0.
PE01RP[3:0]
PE01RN[3:0]
I PCI Express Port 1 Serial Data Receive. Differential PCI Express receive
pairs for port 1. When port 0 is merged with port 1, these signals become
port 0 receive pairs for lanes 4 through 7.
PE01TP[3:0]
PE01TN[3:0]
O PCI Express Port 1 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 1. When port 0 is merged with port 1, these signals
become port 0 transmit pairs for lanes 4 through 7.
PE02RP[3:0]
PE02RN[3:0]
I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pairs for port 2.
PE02TP[3:0]
PE02TN[3:0]
O PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 2.
PE03RP[3:0]
PE03RN[3:0]
I PCI Express Port 3 Serial Data Receive. Differential PCI Express receive
pairs for port 3. When port 2 is merged with port 3, these signals become
port 2 receive pairs for lanes 4 through 7.
PE03TP[3:0]
PE03TN[3:0]
O PCI Express Port 3 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 3. When port 2 is merged with port 3, these signals
become port 2 transmit pairs for lanes 4 through 7.
PE04RP[3:0]
PE04RN[3:0]
I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pairs for port 4.
PE04TP[3:0]
PE04TN[3:0]
O PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 4.
PE05RP[3:0]
PE05RN[3:0]
I PCI Express Port 5 Serial Data Receive. Differential PCI Express receive
pairs for port 5. When port 4 is merged with port 5, these signals become
port 4 receive pairs for lanes 4 through 7.
Table 2 PCI Express Interface Pins (Part 1 of 3)
