89H64H16AG2ZCBLGI Datasheet 89H64H16AG2ZCBLGI, 89H64H16AG2ZCBL, 89H64H16AG2ZCBLI | P19-P21

19 of 62 November 28, 2011

IDT 89HPES64H16AG2 Data Sheet

Pin Characteristics

Note: Some input pads of the switch do not contain internal pull-ups or pull-downs. Unused SMBus and System inputs should be tied off to

appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any

of these pins left floating can cause a slight increase in power consumption. Finally, unused Serdes (Rx and Tx) pins should be left floating.

Function Pin Name Type Buffer

I/O

Type

Internal

Resistor

Notes

PCI Express Interface PE00RN[3:0] I PCIe differ-

ential

Serial Link

PE00RP[3:0] I

PE00TN[3:0] O

PE00TP[3:0] O

PE01RN[3:0] I

PE01RP[3:0] I

PE01TN[3:0] O

PE01TP[3:0] O

PE02RN[3:0] I

PE02RP[3:0] I

PE02TN[3:0] O

PE02TP[3:0] O

PE03RN[3:0] I

PE03RP[3:0] I

PE03TN[3:0] O

PE03TP[3:0] O

PE04RN[3:0] I

PE04RP[3:0] I

PE04TN[3:0] O

PE04TP[3:0] O

PE05RN[3:0] I

PE05RP[3:0] I

PE05TN[3:0] O

PE05TP[3:0] O

PE06RN[3:0] I

PE06RP[3:0] I

PE06TN[3:0] O

PE06TP[3:0] O

PE07RN[3:0] I

PE07RP[3:0] I

PE07TN[3:0] O

PE07TP[3:0] O

PE08RN[3:0] I

PE08RP[3:0] I

PE08TN[3:0] O

Table 9 Pin Characteristics (Part 1 of 3)

20 of 62 November 28, 2011

IDT 89HPES64H16AG2 Data Sheet

PCI Express Interface

(Cont.)

PE08TP[3:0] O PCIe differ-

ential

Serial Link

PE09RN[3:0] I

PE09RP[3:0] I

PE09TN[3:0] O

PE09TP[3:0] O

PE10RN[3:0] I

PE10RP[3:0] I

PE10TN[3:0] O

PE10TP[3:0] O

PE11RN[3:0] I

PE11RP[3:0] I

PE11TN[3:0] O

PE11TP[3:0] O

PE12RN[3:0] I

PE12RP[3:0] I

PE12TN[3:0] O

PE12TP[3:0] O

PE13RN[3:0] I

PE13RP[3:0] I

PE13TN[3:0] O

PE13TP[3:0] O

PE14RN[3:0] I

PE14RP[3:0] I

PE14TN[3:0] O

PE14TP[3:0] O

PE15RN[3:0] I

PE15RP[3:0] I

PE15TN[3:0] O

PE15TP[3:0] O

GCLKN[1:0] I HCSL Diff. Clock

Input

Refer to Table 10

GCLKP[1:0] I

P[15:0]CLKN I

P[15:0]CLKP I

SMBus MSMBADDR[4:1] I LVTTL Input pull-down

MSMBCLK I/O STI

pull-up on board

MSMBDAT I/O STI pull-up on board

SSMBADDR[5,3:1] I Input pull-up

SSMBCLK I/O STI pull-up on board

SSMBDAT I/O STI pull-up on board

Function Pin Name Type Buffer

I/O

Type

Internal

Resistor

Notes

Table 9 Pin Characteristics (Part 2 of 3)

21 of 62 November 28, 2011

IDT 89HPES64H16AG2 Data Sheet

General Purpose I/O GPIO[53:0] I/O LVTTL STI,

High Drive

pull-up

System Pins CLKMODE[1:0] I LVTTL Input pull-up

CLKMODE[2] I pull-down

GCLKFSEL I pull-down

MSMBSMODE I pull-down

P01MERGEN I pull-down

P23MERGEN I pull-down

P45MERGEN I pull-down

P67MERGEN I pull-down

P89MERGEN I pull-down

P1011MERGEN I pull-down

P1213MERGEN I pull-down

P1415MERGEN I pull-down

PERSTN I STI

RSTHALT I Input pull-down

SWMODE[3:0] I pull-down

EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up

JTAG_TDI I STI pull-up

JTAG_TDO O

JTAG_TMS I STI pull-up

JTAG_TRST_N I STI pull-up

SerDes Reference

Resistors

REFRES[15:0] I/O Analog

REFRESPLL I/O

Internal resistor values under typical operating conditions are 92K Ω for pull-up and 91K Ω for pull-down.

All receiver pins set the DC common mode voltage to ground. All transmitters must be AC coupled to the media.

Schmitt Trigger Input (STI).

Function Pin Name Type Buffer

I/O

Type

Internal

Resistor

Notes

Table 9 Pin Characteristics (Part 3 of 3)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57 P58-P60 P61-P62

89H64H16AG2ZCBLGI

Mfr. #:

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Manufacturer:

IDT

Description:

PCI Interface IC PCIE GEN2 SWITCH

Lifecycle:

New from this manufacturer.

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89H64H16AG2ZCBLGI

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