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89H64H16AG2ZCBLGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P62
25 of 62 November 28, 2011
IDT 89HPES64H16AG2 Data Sheet
Figure 5 JTAG AC Timing Waveform
Signal Symbol
Reference
Edge
Min Max Unit
Timing
Diagram
Reference
JTAG
JTAG_TCK Tper_16a none 50.0 — ns See Figure 5.
Thigh_16a,
Tlow_16a
10.0 25.0 ns
JTAG_TMS
1
,
JTAG_TDI
1.
The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
Tsu_16b JTAG_TCK rising 2.4 — ns
Thld_16b 1.0 — ns
JTAG_TDO Tdo_16c JTAG_TCK falling — 20 ns
Tdz_16c
2
2.
The values for this symbol were determined by calculation, not by testing.
—20ns
JTAG_TRST_N Tpw_16d
2
none 25.0 — ns
Table 13 JTAG AC Timing Characteristics
Tpw_16d
Tdz_16cTdo_16c
Thld_16b
Tsu_16b
Thld_16b
Tsu_16b
Tlow_16aTlow_16a
Tper_16a
Thigh_16a
JTAG_TCK
JTAG_TDI
JTAG_TMS
JTAG_TDO
JTAG_TRST_N
26 of 62 November 28, 2011
IDT 89HPES64H16AG2 Data Sheet
Recommended Operating Supply Voltages
Power-Up/Power-Down Sequence
During power supply ramp-up, V
DD
CORE must remain at least 1.0V below V
DD
I/O at all times. There are no other power-up sequence require-
ments for the various operating supply voltages.
The power-down sequence can occur in any order.
Recommended Operating Temperature
Symbol Parameter Minimum Typical Maximum Unit
V
DD
CORE Internal logic supply 0.9 1.0 1.1 V
V
DD
I/O I/O supply except for SerDes 2.25 2.5 2.75 V
3.125 3.3 3.465 V
V
DD
PEA
1
1.
V
DD
PEA and V
DD
PETA should have no more than 25mV
peak-peak
AC power supply noise superimposed on the 1.0V nominal DC value.
PCI Express Analog Power 0.95 1.0 1.1 V
V
DD
PEHA
2
2.
V
DD
PEHA should have no more than 50mV
peak-peak
AC power supply noise superimposed on the 2.5V nominal DC value.
PCI Express Analog High Power 2.25 2.5 2.75 V
V
DD
PETA
1
PCI Express Transmitter Analog Voltage 0.95 1.0 1.1 V
V
SS
Common ground 0 0 0 V
Table 14 PES64H16AG2 Operating Voltages
Grade Temperature
Commercial 0
°C to +70°C Ambient
Industrial -40°C to +85°C Ambient
Table 15 PES64H16AG2 Operating Temperatures
27 of 62 November 28, 2011
IDT 89HPES64H16AG2 Data Sheet
Power Consumption
Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 14
(and also listed below).
Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in
Table 14 (and also listed below).
Note 1: I/O supply of 3.3V is preferred.
Note 2: The above power consumption assumes that all ports are functioning at Gen2 (5.0 GT/S) speeds. Power consumption can be
reduced by turning off unused ports through software or through boot EEPROM. Power savings will occur in V
DD
PEA, V
DD
PEHA, and
V
DD
PETA. Power savings can be estimated as directly proportional to the number of unused ports, since the power consumption of a turned-
off port is close to zero. For example, if 3 ports out of 16 are turned off, then the power savings for each of the above three power rails can be
calculated quite simply as 3/16 multiplied by the power consumption indicated in the above table.
Note 3: Using a port in Gen1 mode (2.5GT/S) results in approximately 18% power savings for each power rail: V
DD
PEA, V
DD
PEHA, and
V
DD
PETA.
Number of Active
Lanes per Port
Core Supply
PCIe Analog
Supply
PCIe Analog
High Supply
PCIe
Transmitter
Supply
I/O Supply Total
Typ
1.0V
Max
1.1V
Typ
1.0V
Max
1.1V
Typ
2.5V
Max
2.75V
Typ
1.0V
Max
1.1V
Typ
2.5V
Max
2.75V
Typ
Power
Max
Power
8/8/8/8/8/8/8/8
(Full Swing)
mA 3900 6275 2621 2875 847 872 1092 1172 32 40
Watts 3.90 6.90 2.62 3.16 2.12 2.40 1.09 1.29 0.08 0.11 9.81 13.86
8/8/8/8/8/8/8/8
(Half Swing)
mA 3900 6275 2254 2472 847 872 568 609 32 40
Watts 3.90 6.90 2.25 2.72 2.12 2.40 0.57 0.67 0.08 0.11 8.92 12.80
Table 16 PES64H16AG2 Power Consumption — 2.5V I/O
Number of Active
Lanes per Port
Core Supply
PCIe Analog
Supply
PCIe Analog
High Supply
PCIe
Transmitter
Supply
I/O Supply Total
Typ
1.0V
Max
1.1V
Typ
1.0V
Max
1.1V
Typ
2.5V
Max
2.75V
Typ
1.0V
Max
1.1V
Typ
3.3V
Max
3.465V
Typ
Power
Max
Power
8/8/8/8/8/8/8/8
(Full Swing)
mA 3900 6275 2621 2875 847 872 1092 1172 36 46
Watts 3.90 6.90 2.62 3.16 2.12 2.40 1.09 1.29 0.12 0.16 9.85 13.91
8/8/8/8/8/8/8/8
(Half Swing)
mA 3900 6275 2254 2472 847 872 568 609 36 46
Watts 3.90 6.90 2.25 2.72 2.12 2.40 0.57 0.67 0.12 0.16 8.96 12.85
Table 17 PES64H16AG2 Power Consumption — 3.3V I/O
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P62

89H64H16AG2ZCBLGI

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IDT
Description:
PCI Interface IC PCIE GEN2 SWITCH
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New from this manufacturer.
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