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AD7475ARMZ-REEL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
Data Sheet AD7475/AD7495
Rev. C | Page 13 of 24
THEORY OF OPERATION
The AD7475/AD7495 are fast, micropower, 12-bit, single-
supply analog-to-digital converters (ADCs). The devices can be
operated from a 2.7 V to 5.25 V supply. When operated from
either a 5 V supply or a 3 V supply, the AD7475/AD7495 are
capable of throughput rates of 1 MSPS when provided with a
20 MHz clock.
The AD7475/AD7495 ADCs have an on-chip track-and-hold
with a serial interface housed in either an 8-lead SOIC or MSOP
package, features that offer the user considerable space-saving
advantages over alternative solutions. The AD7495 also has an
on-chip 2.5 V reference. The serial clock input accesses data from
the device but also provides the clock source for the successive-
approximation ADC. The analog input range is 0 V to REF IN
for the AD7475 and 0 V to REF OUT for the AD7495.
The AD7475/AD7495 also feature power-down options to allow
power saving between conversions. The power-down feature is
implemented across the standard serial interface, as described
in the Operating Modes section.
CONVERTER OPERATION
The AD7475/AD7495 are 12-bit, successive approximation
analog-to-digital converters based around a capacitive DAC.
The AD7475/AD7495 can convert analog input signals in the
range 0 V to 2.5 V. Figure 10 and Figure 12 show simplified
schematics of the ADC. The ADC comprises control logic, SAR,
and a capacitive DAC, which are used to add and subtract fixed
amounts of charge from the sampling capacitor to bring the
comparator back into a balanced condition. Figure 10 shows the
ADC during its acquisition phase. SW2 is closed and SW1 is in
Position A. The comparator is held in a balanced condition and
the sampling capacitor acquires the signal on V
IN
.
COMPARATOR
V
IN
CONTROL LOGIC
CAPACITIVE
DAC
AGND
4k
SW2
SW1
A
B
01684-B-010
Figure 10. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 11), SW2 opens
and SW1 moves to Position B causing the comparator to become
unbalanced. The control logic and the capacitive DAC are used
to add and subtract fixed amounts of charge from the sampling
capacitor to bring the comparator back into a balanced condition.
When the comparator is rebalanced, the conversion is complete.
The control logic generates the ADC output code.
COMPARATOR
V
IN
CONTROL LOGIC
CAPACITIVE
DAC
AGND
4k
SW2
SW1
A
B
01684-B-011
Figure 11. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding of the AD7475/AD7495 is straight binary.
The designed code transitions occur midway between successive
LSB integer values (that is,
1
/
2
LSB and
3
/
2
LSBs). The LSB size
is = V
REF
/4096. The ideal transfer characteristic for the
AD7475/AD7495 is shown in Figure 12.
111...111
111...110
111...000
011...111
000...010
000...001
000...000
ADC CODE
0V
0.5LSB
V
REF
–1.5LSB
ANALOG INPUT
1LSB = V
REF
/4096
01684-B-012
Figure 12. AD7475/AD7495 Transfer Characteristic
AD7475/AD7495 Data Sheet
Rev. C | Page 14 of 24
TYPICAL CONNECTION DIAGRAM
Figure 13 and Figure 15 show typical connection diagrams for
the AD7475 and AD7495, respectively. In both setups, the GND
pin is connected to the analog ground plane of the system. In
Figure 13, REF IN is connected to a decoupled 2.5 V supply
from a reference source, the AD780, to provide an analog input
range of 0 V to 2.5 V. Although the AD7475 connects to a V
DD
of 5 V, the serial interface connects to a 3 V microprocessor. The
V
DRIVE
pin of the AD7475 connects to the same 3 V supply of
the microprocessor to allow a 3 V logic interface (see the Digital
Inputs section.) In Figure 15, the REF OUT pin of the AD7495
is connected to a buffer and then applied to a level-shifting
circuit used on the analog input to allow a bipolar signal to be
applied to the AD7495. A minimum 100 nF capacitance is
required on the REF OUT pin to GND. The conversion result
from both ADCs is output in a 16-bit word with four leading
zeros followed by the MSB of the 12-bit result. For applications
where power consumption is of concern, use the power-down
modes between conversions or bursts of several conversions to
improve power performance. See the Operating Modes section
for more information.
V
DD
V
IN
GND
5V
SUPPLY
2.5V
AD780
3V
SUPPLY
AD7475
0V TO
2.5V
INPUT
SDATA
µ
C/
µ
P
SCLK
SERIAL
INTERFACE
0.1
µ
F
(MIN)
V
DRIVE
REF IN
0.1
µ
F 10
µ
F
0.1
µ
F
10
µ
F
CS
01684-B-013
Figure 13. AD7475 Typical Connection Diagram
Analog Input
Figure 14 shows an equivalent circuit of the analog input
structure of the AD7475/AD7495. The D1 and D2 diodes
provide ESD protection for the analog inputs. Ensure that the
analog input signal never exceeds the supply rails by more than
200 mV. This causes these diodes to become forward-biased
and start conducting current into the substrate. The maximum
current these diodes can conduct without causing irreversible
damage to the device is 20 mA. The capacitor C1 in Figure 14 is
typically about 4 pF and is attributed to pin capacitance. The
resistor R1 is a lumped component made up of the on resistance
of a switch. This resistor is typically about 100 Ω. The capacitor
C2 is the ADC sampling capacitor and has a capacitance of 16
pF, typically. For ac applications, it is recommended to remove
high frequency components from the analog input signal using
an RC low-pass filter on the relevant analog input pin. In
applications where harmonic distortion and signal-to-noise
ratio are critical, drive the analog input from a low impedance
source. Large source impedances significantly affect the ac
performance of the ADC. This may necessitate the use of an
input buffer amplifier. The choice of the op amp is a function of
the particular application.
R1
V
IN
C2
16pF
D1
D2
C1
4pF
V
DD
CONVERSION PHASE: SWITCH OPEN
TRACK PHASE: SWITCH CLOSED
01684-B-014
Figure 14. Equivalent Analog Input Circuit
V
DD
V
IN
GND
5V
SUPPLY
3V
SUPPLY
AD7495
0V TO
2.5V
INPUT
SDATA
µC/µP
SCLK
SERIAL
INTERFACE
0.1µF
(MIN)
V
DRIVE
REF OUT
0.1µF 10µF
0.1µF 10µF
R
R
3R
R
V0V
V
CS
01684-B-015
Figure 15. AD7495 Typical Connection Diagram
Data Sheet AD7475/AD7495
Rev. C | Page 15 of 24
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance depends on the amount of total harmonic
distortion (THD) that can be tolerated. The THD increases as
the source impedance increases and performance degrades.
Figure 16 shows a graph of the total harmonic distortion vs.
source impedance for various analog input frequencies.
SOURCE IMPEDANCE (
Ω
)
–90
THD (dB)
1
100
–80
–70
–60
–50
10000
–40
f
IN
= 500kHz
f
IN
= 10kHz
f
IN
= 100kHz
f
IN
= 200kHz
10 1000
–30
–
20
–10
01684-B-016
Figure 16. THD vs. Source Impedance for Various Analog Input Frequencies
Figure 17 shows a graph of total harmonic distortion vs. analog
input frequency for various supply voltages while sampling at
1 MSPS with an SCLK of 20 MHz.
INPUT FREQUENCY (kHz)
THD (dB)
10 100
–95
–93
–91
–87
1000
–85
V
DD
= V
DRIVE
= 3.60V
V
DD
= V
DRIVE
= 2.70V
V
DD
= V
DRIVE
= 5.25V
V
DD
= V
DRIVE
= 4.75V
–83
–81
–
79
–77
–75
–89
01684-B-017
Figure 17. THD vs. Analog Input Frequency for Various Supply Voltages
Digital Inputs
The digital inputs applied to the AD7475/AD7495 are not limited
by the maximum ratings, which limit the analog inputs. Instead,
the digital inputs applied can go to 7 V and are not restricted by
the V
DD
+ 0.3 V limit as on the analog inputs. Another advantage
of SCLK and
CS
not being restricted by the V
DD
+ 0.3 V limit is
that power supply sequencing issues are avoided.
If
CS
or SCLK are applied before V
DD
, there is no risk of latch-up
as there would be on the analog inputs if a signal greater than
0.3 V were applied prior to V
DD
.
V
DRIVE
The AD7475/AD7495 also has the V
DRIVE
feature. This feature
controls the voltage at which the serial interface operates. V
DRIVE
allows the ADC to easily interface to both 3 V and 5 V processors.
For example, if the AD7475/AD7495 were operated with a V
DD
of 5 V, t h e V
DRIVE
pin could be powered from a 3 V supply. The
AD7475/AD7495 have better dynamic performance with a V
DD
of 5 V, while still being able to interface to 3 V digital devices.
Ensure V
DRIVE
does not exceed V
DD
by more than 0.3 V. (See the
Absolute Maximum Ratings section.)
Reference Section
Use an external reference source to supply the 2.5 V reference to
the AD7475. Errors in the reference source result in gain errors
in the AD7475 transfer function and add the specified full-scale
errors on the device. The AD7475 voltage reference input, REF IN,
has a dynamic input impedance. A small dynamic current is
required to charge the capacitors in the capacitive DAC during
the bit trials. This current is typically 50 µA for a 2.5 V reference.
Place a capacitor of at least 0.1 µF on the REF IN pin. Suitable
reference sources for the AD7475 are the AD780, AD680,
AD1582, ADR391, ADR381, ADR431, and ADR03.
The AD7495 contains an on-chip 2.5 V reference. As shown in
Figure 18, the voltage that appears at the REF OUT pin internally
buffers before applied to the ADC; the output impedance of this
buffer is typically 10 Ω. The reference is capable of sourcing up to
2 mA. Decouple the REF OUT pin to AGND using a 100 nF or
greater capacitor.
If the 2.5 V internal reference is used to drive another device
that is capable of glitching the reference at critical times, then
the reference has to be buffered before driving the device. To
ensure optimum performance of the AD7495, it is recommended
that the internal reference not be over driven. If an ADC with
external reference capability is required, use the AD7475.
V
REF OUT
25Ω
40kΩ
160kΩ
01684-B-018
Figure 18. AD7495 Reference Circuit
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

AD7475ARMZ-REEL7

Mfr. #:
Buy AD7475ARMZ-REEL7
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC IC 1 MSPS 12-Bit
Lifecycle:
New from this manufacturer.
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