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AD7475ARMZ-REEL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
Data Sheet AD7475/AD7495
Rev. C | Page 19 of 24
POWER VS. THROUGHPUT RATE
By using the partial power-down mode on the AD7475/AD7495
when not converting, the average power consumption of the ADC
decreases at lower throughput rates. Figure 24 shows how, as the
throughput rate is reduced, the device remains in its partial power-
down state longer and the average power consumption over
time drops accordingly.
THROUGHPUT (kSPS)
100
0.001
0
POWER (mW)
50 100
0.01
0.1
1
10
150 200 250 300 350
AD7495 5V
SCLK = 20MHz
AD7495 3V
SCLK = 20MHz
AD7475 5V
SCLK = 20MHz
AD7475 3V
SCLK = 20MHz
01684-B-025
Figure 24. Power vs. Throughput for Partial Power Down
For example, if the AD7495 is operated in a continuous
sampling mode with a throughput rate of 100 kSPS and an
SCLK of 20 MHz (V
DD
= 5 V), and the device is placed in partial
power-down mode between conversions, then the power
consumption is calculated as follows. The maximum power
dissipation during normal operation is 13 mW (V
DD
= 5 V). If
the power-up time from partial power-down is one dummy
cycle, that is, 1 μs, and the remaining conversion time is another
cycle, that is, 1 μs, then the AD7495 can be said to dissipate
13 mW for 2 μs during each conversion cycle. For the remainder of
the conversion cycle, 8 μs, the device remains in partial power-
down mode. The AD7495 dissipates 1.15 mW for the remaining
8 μs of the conversion cycle. If the throughput rate is 100 kSPS,
and the cycle time is 10 μs, the average power dissipated during
each cycle is (2/10) × (13 mW) + (8/10) × (1.15 mW) = 3.52 mW. If
V
DD
= 3 V, SCLK = 20 MHz and the device is again in partial
power-down mode between conversions, the power dissipated
during normal operation is 6 mW.
The AD7495 dissipates 6 mW for 2 μs during each conversion
cycle and 0.69 mW for the remaining 8 μs where the device is in
partial power-down. With a throughput rate of 100 kSPS, the
average power dissipated during each conversion cycle is (2/10) ×
(6 mW) + (8/10) × (0.69 mW) = 1.752 mW. Figure 24 shows the
power vs. throughput rate when using partial power-down mode
between conversions with both 5 V and 3 V supplies for both the
AD7475 and AD7495. For the AD7475, partial power-down
current is lower than that of the AD7495.
Full power-down mode is intended for use in applications with
slower throughput rates than required for partial power-down
mode. It is necessary to leave 650 μs for the AD7495 to be fully
powered up from full power-down before initiating a conversion.
Current consumptions between conversions is typically less
than 1 μA.
Figure 25 shows a typical graph of current vs. throughput for
the AD7495 while operating in different modes. At slower
throughput rates, for example, 10 SPS to 1 kSPS, the AD7495
was operated in full power-down mode. As the throughput rate
increased, up to 100 kSPS, the AD7495 was operated in partial
power-down mode, with the device being powered down between
conversions. With throughput rates from 100 kSPS to 1 MSPS,
the device operated in normal mode, remaining fully powered
up at all times.
THROUGHPUT (SPS)
2.0
10
CURRENT (mA)
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
100 1k 10k 100k 1M
V
DD
= 5V
FULL
POWER-DOWN
PARTIAL
POWER-DOWN
NORMAL
01684-B-026
Figure 25. Typical AD7495 Current vs. Throughput
AD7475/AD7495 Data Sheet
Rev. C | Page 20 of 24
SERIAL INTERFACE
Figure 26 shows the detailed timing diagram for serial interfacing
to the AD7475/AD7495. The serial clock provides the conversion
clock and controls the transfer of information from the
AD7475/AD7495 during conversion.
CS
initiates the data transfer and conversion process. The falling
edge of
CS
puts the track-and-hold into hold mode and takes
the bus out of three-state. The analog input is sampled at this point.
The conversion is also initiated at this point and requires 16 SCLK
cycles to complete. Once 13 SCLK falling edges have elapsed,
the track-and-hold goes back into track on the next SCLK rising
edge, as shown in Figure 26 at Point B. On the 16
th
SCLK falling
edge, the SDATA line goes back into three-state. If the rising
edge of
CS
occurs before 16 SCLKs have elapsed, the conversion
is terminated and the SDATA line goes back into three-state, as
shown in Figure 27; otherwise SDATA returns to three-state on
the 16
th
SCLK falling edge, as shown in Figure 26.
Sixteen serial clock cycles are required to perform the
conversion process and to access data from the AD7475/AD7495.
CS
going low provides the first leading zero to be read in by the
microcontroller or DSP. The remaining data is then clocked out
by subsequent SCLK falling edges beginning with the second
leading zero; thus the first falling clock edge on the serial clock
has the second leading zero provided. The final bit in the data
transfer is valid on the 16
th
falling edge, having been clocked out
on the previous (15
th
) falling edge.
In applications with a slower SCLK, it may be possible to read in
data on each SCLK rising edge, although the first leading zero
still has to be read on the first SCLK falling edge after the
CS
falling edge. Therefore, the first rising edge of SCLK after the
CS
falling edge provides the second leading zero and the 15
th
rising SCLK edge has DB0 provided. This method may not
work with most microprocessors/DSPs, but could be used with
FPGAs and ASICs.
SCLK
1
5
13
15
SDATA
FOUR LEADING ZEROS
THREE-STATE
t
4
2
3
16
t
5
t
3
t
QUIET
t
CONVERT
t
2
THREE-STATE
DB11 DB10
DB2
DB0
t
6
t
7
t
8
14
0
0
00
B
DB1
4
01684-B-027
CS
Figure 26. Serial Interface Timing Diagram
SCLK
1
5
13
15
SDAT
A
FOUR LEADING ZEROS
THREE-STATE
t
4
2
3
16
t
9
t
3
t
QUIET
t
CONVERT
t
2
THREE-STATE
DB11 DB10
DB2
t
6
t
7
14
0
0 0
0
B
4
01684-B-028
CS
Figure 27. Serial Interface Timing Diagram — Conversion Termination
Data Sheet AD7475/AD7495
Rev. C | Page 21 of 24
MICROPROCESSOR INTERFACING
The serial interface on the AD7475/AD7495 allows the devices to
directly connect to a range of many different microprocessors. This
section explains how to interface the AD7475/AD7495 with
some of the more common microcontroller and DSP serial
interface protocols.
AD7475/AD7495 TO TMS320C5X/C54X
The serial interface on the TMS320C5x/C54x uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
AD7475/AD7495. The
CS
input allows easy interfacing between
the TMS320C5x/C54x and the AD7475/AD7495 without any
glue logic required. The serial port of the TMS320C5x/C54x is
set up to operate in burst mode with internal CLKX (Tx serial
clock) and FSX (Tx frame sync). The serial port control register
(SPC) must have the following setup: FO = 0, FSM = 1, MCM = 1,
and TXM = 1. The format bit, FO, may be set to 1 to set the
word length to 8 bits, in order to implement the power-down
modes on the AD7475/AD7495.
The connection diagram shown in Figure 28. Note that for
signal processing applications, it is imperative that the frame
synchronization signal from the TMS320C5x/C54x provide
equidistant sampling. The V
DRIVE
pin of the AD7475/AD7495
takes the same supply voltage as that of the TMS320C5x/C54x.
This allows the ADC to operate at a higher voltage than the
serial interface, that is, TMS320C5x/C54x, if necessary.
AD7475/AD7495
*
SCLK
*
ADDITIONAL PINS OMITTED FOR CLARITY
CLKX
DR
FBX
FSR
SDATA
V
DRIVE
V
DD
TMS320C5x/C54x*
CLKR
01684-B-029
CS
Figure 28. Interfacing to the TMS320C5x/54x
AD7475/AD7495 TO ADSP-21xx
The ADSP-21xx family of DSPs interfaces directly to the
AD7475/AD7495 without any glue logic required. The V
DRIVE
pin of the AD7475/AD7495 takes the same supply voltage as
that of the ADSP-21xx. This allows the ADC to operate at a
higher voltage than the serial interface, that is, ADSP-21xx, if
necessary.
The SPORT control register should be set up as shown in Table 6.
Table 6.
SPORT Control Register Bits Function
TFSW = RFSW = 1 Alternate framing
INVRFS = INVTFS = 1 Active low frame signal
DTYPE = 00 Right-justify data
SLEN = 1111 16-bit data words
ISCLK = 1
Internal serial clock
TFSR = RFSR = 1 Frame every word
IRFS = 0
ITFS = 1
To implement the power-down modes, SLEN should be set to
1001 to issue an 8-bit SCLK burst.
The connection diagram is shown in Figure 29. The ADSP-21xx
has the TFS and RFS of the SPORT tied together, with TFS set
as an output and RFS set as an input. The DSP operates in
alternate framing mode and the SPORT control register is set up
as described. The frame synchronization signal generated on the
TFS is tied to
CS
and, as with all signal processing applications,
equidistant sampling is necessary. However, in this example, the
timer interrupt is used to control the sampling rate of the ADC
and; under certain conditions, equidistant sampling may not be
achieved.
AD7475/AD7495*
SCLK
*
ADDITIONAL PINS OMITTED FOR CLARITY
DR
RFS
TFS
SDATA
V
DRIVE
V
DD
ADSP-21xx
*
SCLK
01684-B-030
CS
Figure 29. Interfacing to the ADSP-21xx
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

AD7475ARMZ-REEL7

Mfr. #:
Buy AD7475ARMZ-REEL7
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC IC 1 MSPS 12-Bit
Lifecycle:
New from this manufacturer.
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