Data Sheet AD7475/AD7495
Rev. C | Page 7 of 24
TIMING SPECIFICATIONS
1
V
DD
= 2.7 V to 5.25 V, V
DRIVE
= 2.7 V to 5.25 V, REF IN = 2.5 V (AD7475), T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter Limit at T
MIN
, T
MAX
Unit Description
f
SCLK
2
10 kHz min
20 MHz max
t
CONVERT
16 × t
SCLK
t
SCLK
= 1/f
SCLK
800 ns max f
SCLK
= 20 MHz
t
QUIET
100 ns min Minimum quiet time required between conversions
t
2
10 ns min
CS
to SCLK setup time
t
3
3
22 ns max Delay from
CS
until SDATA three-state disabled
t
4
3
40 ns max Data access time after SCLK falling edge
t
5
0.4 t
SCLK
ns min SCLK low pulse width
t
6
0.4 t
SCLK
ns min SCLK high pulse width
t
7
10 ns min SCLK to data valid hold time
t
8
4
10 ns min SCLK falling edge to SDATA high impedance
45 ns max SCLK falling edge to SDATA high impedance
t
9
4
20 ns max
CS
rising edge to SDATA high impedance
t
POWER-UP
20 µs max Power-up time from full power-down (AD7475)
650 µs max Power-up time from full power-down (AD7495)
1
Guaranteed by initial characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DRIVE
) and timed from a voltage level of 1.6 V.
2
Mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 4 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4
t
8
and t
9
are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured number is
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times, t
8
and t
9
, quoted in the timing characteristics are
the true bus relinquish times of the device and are independent of the bus loading.
