AD7475/AD7495 Data Sheet
Rev. C | Page 22 of 24
The timer registers are loaded with a value that provides an
interrupt at the required sample interval. When an interrupt is
received, a value is transmitted with TFS/DT (ADC control
word). The TFS is used to control the RFS, and therefore, the
reading of data. The frequency of the serial clock is set in the
SCLKDIV register. When the instruction to transmit with TFS
is given, (that is, AX0 = TX0), the state of the SCLK is checked.
The DSP waits until the SCLK has gone high, low, and high
before transmission starts. If the timer and SCLK values are
chosen such that the instruction to transmit occurs on or near
the rising edge of SCLK, the data can be transmitted or it can
wait until the next clock edge.
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3, an
SCLK of 2 MHz is obtained, and eight master clock periods
elapse for every one SCLK period. If the timer registers are loaded
with the value 803, 100.5 SCLKs occur between interrupts and
subsequently between transmit instructions. This situation results
in nonequidistant sampling because the transmit instruction is
occurring on a SCLK edge. If the number of SCLKs between
interrupts is a whole integer figure of N, equidistant sampling is
implemented by the DSP.
AD7475/AD7495 TO DSP56XXX
The connection diagram in Figure 30 shows how the
AD7475/AD7495 connects to the synchronous serial interface
(SSI) of the DSP56xxx family of devices from Motorola. The SSI is
operated in synchronous mode (SYN bit in CRB = 1) with
internally generated 1-bit clock period frame sync for both Tx
and Rx (Bits FSL1 = 1 and FSL0 = 0 in CRB). Set the word
length to 16 by setting Bits WL1 = 1 and WL0 = 0 in CRA. To
implement the power-down modes on the AD7475/AD7495,
the word length can be changed to 8 bits by setting Bit WL1 = 0
and Bit WL0 = 0 in CRA. For signal processing applications, it
is imperative that the frame synchronization signal from the
DSP56xxx provide equidistant sampling. The V
DRIVE
pin of the
AD7475/AD7495 takes the same supply voltage as that of the
DSP56xxx. This allows the ADC to operate at a voltage higher
than the serial interface, that is, DSP56xxx, if necessary.
AD7475/AD7495*
SCLK
*
ADDITIONAL PINS OMITTED FOR CLARITY
SCLK
SC2
SDATA
V
DRIVE
V
DD
DSP56xxx*
SRD
01684-B-031
CS
Figure 30. Interfacing to the DSP56xxx
AD7475/AD7495 TO MC68HC16
The serial peripheral interface (SPI) on the MC68HC16 is
configured for master mode (MSTR) = 1, clock polarity bit
(CPOL) = 1, and the clock phase bit (CPHA) = 0. The SPI is
configured by writing to the SPI control register (SPCR), as
described in the 68HC16 User Manual. The serial transfer takes
place as a 16-bit operation when the size bit in the SPCR register is
set to size = 1. To implement the power-down modes with an 8-bit
transfer, set size = 0. (A connection diagram is shown in Figure 31.)
The V
DRIVE
pin of the AD7475/AD7495 takes the same supply
voltage as that of the MC68HC16. This allows the ADC to
operate at a higher voltage than the serial interface, that is, the
MC68HC16, if necessary.
AD7475/AD7495*
SCLK
*
ADDITIONAL PINS OMITTED FOR CLARITY
MISO/PMC0
SS/PMC3
SDATA
V
DRIVE
V
DD
MC68HC16
*
SCLK/PCM2
01684-B-032
CS
Figure 31. Interfacing to the MC68HC16
