AD7475/AD7495 Data Sheet
Rev. C | Page 18 of 24
Full power-down is entered in a way similar to partial power-
down, except the timing sequence shown in Figure 20 must be
executed twice. The conversion process must be interrupted in a
similar fashion by bringing
CS
high anywhere after the second
falling edge of SCLK and before the 10
th
falling edge of SCLK.
The device enters partial power-down at this point. To reach full
power-down, interrupt the next conversion cycle in the same
way, as shown in Figure 22. Once
CS
has been brought high in
this window of SCLKs, then the device powers down completely.
Note that it is not necessary to complete the 16 SCLKs once
CS
has been brought high to enter a power-down mode.
To exit full power-down, and power up the AD7475/AD7495
again, a dummy conversion is performed as when powering up
from partial power-down. On the falling edge of
CS
, the device
begins to power up and continues to power up as long as
CS
is
held low until after the falling edge of the 10
th
SCLK. The power-up
time is longer than one dummy conversion cycle however, and
this time, t
POWER-UP,
must elapse before a conversion can be initiated,
as shown in Figure 23. See the Timing Specifications section for
more information.
When power supplies are first applied to the AD7475/AD7495,
the ADC may power up in either of the power-down modes or
normal mode. Because of this, it is best to allow a dummy cycle
to elapse to ensure the device is fully powered up before attempting
a valid conversion. Likewise, if the intent is to keep the device in
partial power-down mode immediately after the supplies are
applied, then two dummy cycles must be initiated.
The first dummy cycle must hold
CS
low until after the 10
th
SCLK
falling edge, as shown in Figure 19. In the second cycle, bring
CS
high before the 10
th
SCLK edge, but after the second SCLK
falling edge, as shown in Figure 20. Alternatively, if the intent is to
place the device in full power-down mode when the supplies
have been applied, then three dummy cycles must be initiated.
The first dummy cycle must hold
CS
low until after the 10
th
SCLK
edge, as shown in Figure 19; the second and third dummy cycle
place the device in full power-down, as shown in Figure 22. (See
the Operating Modes section.) Once supplies are applied to the
AD7475, allow enough time for the external reference to power
up and charge the reference capacitor to its final value. For the
AD7495, allow enough time for the internal reference buffer to
charge the reference capacitor. Then, to place the AD7475/AD7495
in normal mode, initiate a dummy cycle, 1 μs. If the first valid
conversion is performed directly after the dummy conversion,
allow adequate acquisition time. As mentioned earlier, when
powering up from the power-down mode, the device returns to
track upon the first SCLK edge applied after the falling edge of
CS
. However, when the ADC powers up initially after supplies
are applied, the track-and-hold is already in track. This means
(assuming one has the facility to monitor the ADC supply current)
if the ADC powers up in the desired mode of operation, and a
dummy cycle is not required to change mode, then neither is a
dummy cycle required to place the track-and-hold into track. If
no current monitoring facility is available, perform the relevant
dummy cycle or cycles to ensure the device is in the required mode.
SCLK
SDATA
INVALID DATA
VALID DATA
1
10
16
1
THE PART BEGINS
TO POWER UP
THE PART IS FULLY
POWERED UP
16
t
POWER-UP
01684-B-022
CS
Figure 23. Exiting Full Power-Down Mode
