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NCP81119MNTXG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
NCP81119
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13
Table 1. VR12.5 VID CODES
VID7 HEX
Voltage
(V)
VID0VID1VID2VID3VID4VID5VID6
1 0 0 0 0 1 1 1 1.84 87
1 0 0 0 1 0 0 0 1.85 88
1 0 0 0 1 0 0 1 1.86 89
1 0 0 0 1 0 1 0 1.87 8A
1 0 0 0 1 0 1 1 1.88 8B
1 0 0 0 1 1 0 0 1.89 8C
1 0 0 0 1 1 0 1 1.9 8D
1 0 0 0 1 1 1 0 1.91 8E
1 0 0 0 1 1 1 1 1.92 8F
1 0 0 1 0 0 0 0 1.93 90
1 0 0 1 0 0 0 1 1.94 91
1 0 0 1 0 0 1 0 1.95 92
1 0 0 1 0 0 1 1 1.96 93
1 0 0 1 0 1 0 0 1.97 94
1 0 0 1 0 1 0 1 1.98 95
1 0 0 1 0 1 1 0 1.99 96
1 0 0 1 0 1 1 1 2 97
1 0 0 1 1 0 0 0 2.01 98
1 0 0 1 1 0 0 1 2.02 99
1 0 0 1 1 0 1 0 2.03 9A
1 0 0 1 1 0 1 1 2.04 9B
1 0 0 1 1 1 0 0 2.05 9C
1 0 0 1 1 1 0 1 2.06 9D
1 0 0 1 1 1 1 0 2.07 9E
1 0 0 1 1 1 1 1 2.08 9F
1 0 1 0 0 0 0 0 2.09 A0
1 0 1 0 0 0 0 1 2.1 A1
1 0 1 0 0 0 1 0 2.11 A2
1 0 1 0 0 0 1 1 2.12 A3
1 0 1 0 0 1 0 0 2.13 A4
1 0 1 0 0 1 0 1 2.14 A5
1 0 1 0 0 1 1 0 2.15 A6
1 0 1 0 0 1 1 1 2.16 A7
1 0 1 0 1 0 0 0 2.17 A8
1 0 1 0 1 0 0 1 2.18 A9
1 0 1 0 1 0 1 0 2.19 AA
1 0 1 0 1 0 1 1 2.2 AB
1 0 1 0 1 1 0 0 2.21 AC
1 0 1 0 1 1 0 1 2.22 AD
1 0 1 0 1 1 1 0 2.23 AE
1 0 1 0 1 1 1 1 2.24 AF
NCP81119
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14
Table 1. VR12.5 VID CODES
VID7 HEX
Voltage
(V)
VID0VID1VID2VID3VID4VID5VID6
1 0 1 1 0 0 0 0 2.25 B0
1 0 1 1 0 0 0 1 2.26 B1
1 0 1 1 0 0 1 0 2.27 B2
1 0 1 1 0 0 1 1 2.28 B3
1 0 1 1 0 1 0 0 2.29 B4
1 0 1 1 0 1 0 1 2.3 B5
SVID Bus Idle
Figure 3. SVID Timing Diagram
VCC
VR12.6 EN
VSP
VR_RDY
SVID ALERT
SVC
SVD
TA
TB
VBOOT
TC
Status PKT
Description Min Typ Max Unit
T
A
1
5 mS
T
B
1
10
mV/mS
T
C
1
0 6
mS
T
D
1
External Enable de-assert to recognition of de-assert
0 1
mS
T
E
1
Internal Enable de-assert to VR_RDY de-assert
500 nS
NCP81119
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SCLK
SDIO
VR latch
CPU
send
CPU Driving, SIngle Data Rate
SCLK
SDIO
CPU latch
VR
send
VR Driving, Single Data Rate
Figure 4.
T
co_CPU
= clock to data delay in CPU
t
su
= 0.5 * T − T
co_CPU
t
hld
= 0.5 * T + T
co_CPU
T
co_CPU
t
su
t
hld
T
co_CPU
T
co_CPU
= clock to data delay in VR
t
su
= T − 2 * T
fly
− T
co_VR
t
hld
= 2 * T
fly
− T
co_VR
T
fly
propagation time on Serial VID bus
t
su
t
hld
T
co_VR
STATE TRUTH TABLE
STATE VR_RDY Pin
Error AMP
Comp Pin
OVP & UVP DRON Pin
Method of
Reset
POR
0 < VCC < UVLO
N/A N/A N/A Resistive pull down
Disabled
EN < threshold
UVLO > threshold
Low Low Disabled Low
Start up Delay &
Calibration
EN > threshold
UVLO > threshold
Low Low Disabled Low
DRON Fault
EN > threshold
UVLO > threshold
DRON < threshold
Low Low Disabled Resistive pull up Driver must
release DRON
to high
Soft Start
EN > threshold
UVLO > threshold
DRON > High
Low Operational Active /
No latch
High
Normal Operation
EN > threshold
UVLO >threshold
DRON > High
High Operational Active /
Latching
High N/A
Over Voltage Low N/A DAC + 150 mV High
Over Current Low Operational Last DAC Code Low
VID Code = 00h Low: if Reg34h:bit0 = 0;
High:if Reg34h:bit0 = 1
Clamped at
0.9 V
Disabled High, PWM outputs
in low state
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27

NCP81119MNTXG

Mfr. #:
Buy NCP81119MNTXG
Manufacturer:
ON Semiconductor
Description:
Switching Voltage Regulators VR CONTROLLER
Lifecycle:
New from this manufacturer.
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