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NCP81119MNTXG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
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NCP81119 Operating Frequency vs. R
osc
Figure 9. NCP81119 R
osc
vs. Frequency
The oscillator generates triangle ramps that are 0.5~2.5 V in amplitude depending on the VRMP pin voltage to provide input
voltage feed forward compensation. The ramps are equally spaced out of phase with respect to each other.
Programming the Ramp Feed−Forward Circuit
The ramp generator circuit provides the ramp used by the PWM comparators. The ramp generator provides voltage
feed−forward control by varying the ramp magnitude with respect to the VRMP pin voltage. The VRMP pin also has a 4 V
UVLO function. The VRMP UVLO is only active after the controller is enabled. The VRMP pin is high impedance input when
the controller is disabled.
The PWM ramp time is changed according to the following,
V
RAMPpkäpkPP
+ 0.1 * V
VRMP
Vin
Comp−IL
Duty
Vramp_pp
PWM Comparators
The noninverting input of the comparator for each phase is connected to the summed output of the error amplifier (COMP)
and each phase current (I
L
*DCR*Phase Balance Gain Factor). The inverting input is connected to the oscillator ramp voltage
with a 1.3 V offset. The operating input voltage range of the comparators is from 0 V to 3.0 V and the output of the comparator
generates the PWM output.
During steady state operation, the duty cycle is centered on the valley of the sawtooth ramp waveform. The steady state duty
cycle is still calculated by approximately Vout/Vin. During a transient event, the controller will operate in a hysteretic mode
with the duty cycles pull in for all phases as the error amp signal increases with respect to all the ramps.
PHASE DETECTION SEQUENCE
During start−up, the number of operational phases and their phase relationship is determined by the internal circuitry
monitoring the CSN Pins. Normally, NCP81119 operates as a 4−phase Vcore PWM controller. Connecting CSN4 pin to V
CC
programs 3−phase operation, connecting CSN2 and CSN4 pin to V
CC
programs 2−phase operation, connecting CSN2, CSN3
and CSN4 pin to V
CC
programs 1−phase operation. Prior to soft start, while ENABLE is high, CSN4 to CSN2 pins sink
approximately 50 mA. An internal comparator checks the voltage of each pin versus a threshold of 4.5 V. If the pin is tied to
NCP81119
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V
CC
, its voltage is above the threshold. Otherwise, an internal current sink pulls the pin to GND, which is below the threshold.
PWM1 is low during the phase detection interval, which takes 30 ms. After this time, if the remaining CSN outputs are not
pulled to V
CC
, the 50 mA current sink is removed, and NCP81119 functions as normal 4 phase controller. If the CSNs are pulled
to V
CC
, the 50 mA current source is removed, and the outputs are driven into a high impedance state.
The PWM outputs are logic−level devices intended for driving fast response external gate drivers such as the NCP5901 and
NCP5911 .Because each phase is monitored independently, operation approaching 100% duty cycle is possible. In addition,
more than one PWM output can be on at the same time to allow overlapping phases.
PROTECTION FEATURES
Under voltage Lockouts
There are several under voltage monitors in the system. Hysteresis is incorporated within the comparators. NCP81119
monitors the VCC Shunt supply. The gate driver monitors both the gate driver V
CC
and the BST voltage. When the voltage
on the gate driver is insufficient it will pull DRON low and prevents the controller from being enabled. The gate driver will
hold DRON low for a minimum period of time to allow the controller to hold off it’s startup sequence. In this case the PWM
is set to the MID state to begin soft start.
Gate Driver UVLO Restart
Figure 10.
Soft Start
Soft start is implemented internally. A digital counter steps the DAC up from zero to the target voltage based on the
predetermined rate in the spec table. The PWM signals will start out open with a test current to collect data on phase count and
for setting internal registers. After the configuration data is collected, if the controller is enabled the PWMs will be set to 2.0 V
MID state to indicate that the drivers should be in diode mode. DRON will then be asserted. As the DAC ramps the PWM
outputs will begin to fire. Each phase will move out of the MID state when the first PWM pulse is produced. When the controller
is disabled the PWM signal will return to the MID state.
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Figure 11.
Over Current Latch− Off Protection
The NCP81119 compares a programmable current−limit set point to the voltage from the output of the current−summing
amplifier. The level of current limit is set with the resistor from the ILIM pin to CSCOMP. The current through the external
resistor connected between ILIM and CSCOMP is then compared to the internal current limit current I
CL
.
If the current
generated through this resistor into the ILIM pin (Ilim) exceeds the internal current−limit threshold current (I
CL
), an internal
latch−off counter starts, and the controller shuts down if the fault is not removed after 50 ms (shut down immediately for 150%
load current) after which the outputs will remain disabled until the V
CC
voltage or EN is toggled.
On startup a clim1/clim2 current limit protection is enabled once the output voltage has exceeded 250 mV or if the internal
DAC voltage has increased above 300 mV, this allow for protection again a Vout short to ground. This is necessary because
the voltage swing of CSCOMP cannot go below ground. This limits the voltage drop across the DCR through the current
balance circuitry.
The over−current limit is programmed by a resistor on the ILIM pin. The resistor value can be calculated by the following
equation:
R
ILIM
+
I
LIM
* DCR * R
CS
ńR
PH
I
CL
Where I
CL
= 10 mA
R
PH
R
PH
R
CS
RLIM
ILIM
CSCOMP
CSSUM
R
PH
R
PH
CSREF
Figure 12.
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NCP81119MNTXG

Mfr. #:
Buy NCP81119MNTXG
Manufacturer:
ON Semiconductor
Description:
Switching Voltage Regulators VR CONTROLLER
Lifecycle:
New from this manufacturer.
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