1. General description
PTN3366 is a low power, high-speed level shifter device which converts four lanes of
low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.4b compliant
open-drain current-steering differential output signals, up to 3 Gbit/s per lane to support
36-bit deep color mode, 4K 2K video format or 3D video data transport. Each of these
lanes provides a level-shifting differential active buffer, with built-in Equalization, to
translate from low-swing AC-coupled differential signaling on the source side, to
TMDS-type DC-coupled differential current-mode signaling terminated into 50 to 3.3 V
on the sink side. Additionally, the PTN3366 provides a single-ended active buffer for
voltage translation of the HPD signal from 5 V on the sink side to 3.3 V on the source side
and provides a channel with active buffering and level shifting of the DDC channel
(consisting of a clock and a data line) between 3.3 V source-side and 5 V sink-side. The
DDC channel is implemented using active I
2
C-bus buffer technology providing redriving
and level shifting as well as disablement (isolation between source and sink) of the clock
and data lines.
The low-swing AC-coupled differential input signals to the PTN3366 typically come from a
display source with multi-mode I/O, which supports multiple display standards, for
example, DisplayPort, HDMI and DVI. While the input differential signals are configured to
carry DVI or HDMI coded data, they do not comply with the electrical requirements of the
DVI v1.0 or HDMI v1.4b specification. By using PTN3366, chip set vendors are able to
implement such reconfigurable I/Os on multi-mode display source devices, allowing the
support of multiple display standards while keeping the number of chip set I/O pins low.
See Figure 1
.
The PTN3366 main high-speed differential lanes feature low-swing self-biasing differential
inputs which are compliant to the electrical specifications of DisplayPort Standard v1.2a
and/or PCI Express Standard v1.1, and open-drain current-steering differential outputs
compliant to DVI v1.0 and HDMI v1.4b electrical specifications. The I
2
C-bus channel
actively buffers as well as level-translates the DDC signals. The PTN3366 supports
standby mode in order to minimize current consumption when Hot Plug Detect signal
HPD_SINK is LOW.
PTN3366 is powered from a single 3.3 V power supply consuming a small amount of
power (72 mW typical) and is offered in a 32-terminal HVQFN32 package.
PTN3366
Low power HDMI/DVI level shifter with active DDC buffer,
supporting 3 Gbit/s operation
Rev. 1.1 — 22 May 2015 Product data sheet
PTN3366 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1.1 — 22 May 2015 2 of 26
NXP Semiconductors
PTN3366
Low power HDMI/DVI level shifter supporting 3 Gbit/s operation
Remark: TMDS clock and data lanes can be assigned arbitrarily and interchangeably to IN_D[4:1].
Fig 1. Typical HDMI/DVI level shifter application system diagram
002aah583
OUT_D1
OUT_D1+
IN_D1
IN_D1+
HPD_SOURCE HPD_SINK
SCL_SINK
SDA_SINK
DDC_EN
SCL_SOURCE
SDA_SOURCE
OUT_D2
OUT_D2+
IN_D2
IN_D2+
OUT_D3
OUT_D3+
IN_D3
IN_D3+
OUT_D4
OUT_D4+
IN_D4
IN_D4+
PTN3366
OE_N
DVI/HDMI CONNECTOR
5 V
5 V
0 V to 5 V0 V to 3.3 V
3.3 V
3.3 V
3.3 V
AC-coupled
differential pair
clock
CLOCK LANE
DATA LANE
DATA LANE
DATA LANE
AC-coupled
differential pair
TMDS data
AC-coupled
differential pair
TMDS data
AC-coupled
differential pair
TMDS data
TX
TX
FF
TMDS
clock
pattern
MULTI-MODE DISPLAY SOURCE
TX
TX
FF
TMDS
coded
data
TX
TX
FF
TMDS
coded
data
TX
TX
FF
TMDS
coded
data
DP PHY ELECTRICAL
CONFIGURATION
DDC I/O
(I
2
C-bus)
DP
output buffer
reconfigurable I/Os
DP
output buffer
DP
output buffer
DP
output buffer
EQ0/EQ1
binary inputs
PTN3366 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1.1 — 22 May 2015 3 of 26
NXP Semiconductors
PTN3366
Low power HDMI/DVI level shifter supporting 3 Gbit/s operation
2. Features and benefits
2.1 High-speed TMDS level shifting
Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and
HDMI v1.4b compliant open-drain current-steering differential output signals
TMDS level shifting operation up to 3 Gbit/s per lane (300 MHz TMDS clock)
supporting 4K 2K 3 Gbit/s and 3D video formats
Programmable receive equalization
Integrated 50 termination resistors for self-biasing differential inputs
Back-current safe outputs to disallow current when device power is off and monitor is
on
Disable feature to turn off TMDS inputs and outputs and to enter low-power condition
Selectable differential output termination on TMDS channels
2.2 DDC level shifting
Integrated DDC buffering and level shifting (3.3 V source to 5 V sink side and
vice versa)
Rise time accelerator on connector side DDC ports
Up to 400 kHz I
2
C-bus clock frequency
Back-power safe sink-side terminals to disallow backdrive current when power is off or
when DDC is not enabled
2.3 HPD level shifting
HPD non-inverting level shift from 0 V on the sink side to 0 V on the source side, or
from 5 V on the sink side to 3.3 V on the source side
Integrated 200 k pull-down resistor on HPD sink input guarantees ‘input LOW’ when
no display is plugged in
Back-power safe design on HPD_SINK to disallow backdrive current when power is off
2.4 General
Power supply 3.3 V
ESD resilience to 8 kV HBM, 1 kV CDM
Power-saving modes
Back-current-safe design on all sink-side main link, DDC and HPD terminals
Transparent operation: no retiming or software configuration required
32-terminal HVQFN32 package
3. Applications
PC motherboard/graphics card
Docking station

PTN3366BSMP

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Equalizers PTN3366BS/HVQFN32///REEL 13 Q2 DP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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