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PTN3366BSMP

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
PTN3366 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1.1 — 22 May 2015 7 of 26
NXP Semiconductors
PTN3366
Low power HDMI/DVI level shifter supporting 3 Gbit/s operation
IN_D3+ 30 Self-biasing
differential input
Low-swing differential input from display source. IN_D3+ makes a
differential pair with IN_D3. The input to this pin must be AC coupled
externally.
IN_D3 29 Self-biasing
differential input
Low-swing differential input from display source. IN_D3 makes a
differential pair with IN_D3+. The input to this pin must be AC coupled
externally.
IN_D2+ 28 Self-biasing
differential input
Low-swing differential input from display source. IN_D2+ makes a
differential pair with IN_D2. The input to this pin must be AC coupled
externally.
IN_D2 27 Self-biasing
differential input
Low-swing differential input from display source. IN_D2 makes a
differential pair with IN_D2+. The input to this pin must be AC coupled
externally.
IN_D1+ 26 Self-biasing
differential input
Low-swing differential input from display source. IN_D1+ makes a
differential pair with IN_D1. The input to this pin must be AC coupled
externally.
IN_D1 25 Self-biasing
differential input
Low-swing differential input from display source. IN_D1 makes a
differential pair with IN_D1+. The input to this pin must be AC coupled
externally.
OUT_D4+ 9 TMDS differential
output
HDMI-compliant TMDS output. OUT_D4+ makes a differential pair with
OUT_D4. OUT_D4+ is in phase with IN_D4+.
OUT_D4 10 TMDS differential
output
HDMI-compliant TMDS output. OUT_D4 makes a differential pair with
OUT_D4+. OUT_D4 is in phase with IN_D4.
OUT_D3+ 11 TMDS differential
output
HDMI-compliant TMDS output. OUT_D3+ makes a differential pair with
OUT_D3. OUT_D3+ is in phase with IN_D3+.
OUT_D3 12 TMDS differential
output
HDMI-compliant TMDS output. OUT_D3 makes a differential pair with
OUT_D3+. OUT_D3 is in phase with IN_D3.
OUT_D2+ 13 TMDS differential
output
HDMI-compliant TMDS output. OUT_D2+ makes a differential pair with
OUT_D2. OUT_D2+ is in phase with IN_D2+.
OUT_D2 14 TMDS differential
output
HDMI-compliant TMDS output. OUT_D2 makes a differential pair with
OUT_D2+. OUT_D2
is in phase with IN_D2.
OUT
_D1+ 15 TMDS differential
output
HDMI-compliant TMDS output. OUT_D1+ makes a differential pair with
OUT_D1. OUT_D1+ is in phase with IN_D1+.
OUT_D1 16 TMDS differential
output
HDMI-compliant TMDS output. OUT_D1 makes a differential pair with
OUT_D1+. OUT_D1 is in phase with IN_D1.
HPD and DDC signals
HPD_SINK 21 5 V CMOS
single-ended input
0 V to 5 V (nominal) input signal. This signal comes from the DVI or
HDMI sink. A HIGH value indicates that the sink is connected; a LOW
value indicates that the sink is disconnected. HPD_SINK is pulled down
by an integrated 200 k pull-down resistor.
HPD_SOURCE 5 3.3 V CMOS
single-ended output
0 V to 3.3 V (nominal) output signal. This is level-shifted version of the
HPD_SINK signal.
SCL_SOURCE 7 single-ended 3.3 V
open-drain DDC I/O
3.3 V source-side DDC clock I/O. Pulled up by external termination to
3.3 V. 5 V tolerant I/O.
SDA_SOURCE 6 single-ended 3.3 V
open-drain DDC I/O
3.3 V source-side DDC data I/O. Pulled up by external termination to
3.3 V. 5 V tolerant I/O.
SCL_SINK 19 single-ended 5 V
open-drain DDC I/O
5 V sink-side DDC clock I/O. Pulled up by external termination to 5 V.
Provides rise time acceleration for LOW-to-HIGH transitions.
Table 3. Pin description
…continued
Symbol Pin Type Description
PTN3366 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1.1 — 22 May 2015 8 of 26
NXP Semiconductors
PTN3366
Low power HDMI/DVI level shifter supporting 3 Gbit/s operation
[1] HVQFN32 package supply ground is connected to the exposed center pad. The exposed center pad must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad must be soldered
to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias must be
incorporated in the PCB in the thermal pad region.
SDA_SINK 20 single-ended 5 V
open-drain DDC I/O
5 V sink-side DDC data I/O. Pulled up by external termination to 5 V.
Provides rise time acceleration for LOW-to-HIGH transitions.
DDC_EN 22 3.3 V CMOS input Enables the DDC buffer and level shifter.
When DDC_EN = LOW, buffer/level shifter is disabled.
When DDC_EN = HIGH, buffer and level shifter are enabled.
Supply and ground
V
DD
1, 18 3.3 V DC supply Supply voltage; 3.3 V 10 %.
GND
[1]
center
pad
ground Supply ground. The exposed center pad must be connected to system
ground for proper operation.
Feature control signals
REXT 4 analog I/O Current sense port used to provide an accurate current reference for the
differential outputs OUT_Dx. For best output voltage swing accuracy,
use of a 12.4 k resistor (1 % tolerance) from this terminal to GND is
recommended. May also be tied to GND directly (0 ). See Section 7.2
for details.
EQ1 2 3.3 V low-voltage
CMOS inputs
Equalizer setting input pins. These pins can be board-strapped to one
of two decode values: short to GND, short to V
DD
. See Table 5 for truth
table.
EQ0 8
n.c. 3, 23,
24
- Not connected; leave this pin open.
Table 3. Pin description
…continued
Symbol Pin Type Description
PTN3366 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1.1 — 22 May 2015 9 of 26
NXP Semiconductors
PTN3366
Low power HDMI/DVI level shifter supporting 3 Gbit/s operation
7. Functional description
Refer to Figure 2 “Functional diagram of PTN3366”.
The PTN3366 level shifts four lanes of low-swing AC-coupled differential input signals to
DVI and HDMI-compliant open-drain current-steering differential output signals, up to
3 Gbit/s per lane to support 36-bit deep color, 3 Gbit/s and 3D modes. It has integrated
50 termination resistors for AC-coupled differential input signals. An enable signal
OE_N can be used to turn off the TMDS inputs and outputs, thereby minimizing power
consumption to ultra low level. The TMDS outputs are back-power safe to disallow current
flow from a powered sink while the PTN3366 is unpowered.
The PTN3366’s DDC channel provides active level shifting and buffering, allowing 3.3 V
source-side termination and 5 V sink-side termination. The sink-side DDC ports are
equipped with a rise time accelerator enabling drive of long cables or high bus
capacitance. This enables the system designer to isolate bus capacitance to meet/exceed
HDMI DDC specification. The PTN3366 offers back-power safe sink-side I/Os to disallow
backdrive current from the DDC clock and data lines when power is off or when DDC is
not enabled. An enable signal DCC_EN enables the DDC level shifter block.
The PTN3366 also provides voltage translation for the Hot Plug Detect (HPD) signal from
0 V to 5 V on the sink side to 0 V to 3.3 V on the source side.
The PTN3366 does not retime any data. It contains no state machines. No inputs or
outputs of the device are latched or clocked. Because the PTN3366 acts as a transparent
level shifter, no reset is required.
7.1 Enable and disable features
PTN3366 offers different ways to enable or disable functionality, using the Output Enable
(OE_N), and DDC Enable (DDC_EN) inputs. Whenever the PTN3366 is disabled
(OEN = HIGH and DDC_EN = LOW), the device is in Ultra low power mode and power
consumption is ultra low; otherwise the PTN3366 is in active mode and power
consumption depends on level of HPD_SINK signal. These two inputs each affect the
operation of PTN3366 differently: OE_N controls the TMDS channels, DDC_EN controls
only the DDC channel, and HPD_SINK is not affected by either of the control inputs. The
following sections and truth table describe their detailed operation.
7.1.1 Hot plug detect
The HPD channel of PTN3366 functions as a level-shifting buffer to pass the HPD logic
signal from the display sink device (via input HPD_SINK) on to the display source device
(via output HPD_SOURCE). The HPD_SINK level is used to control the power state of the
PTN3366. If HPD_SINK is LOW, then PTN3366 is in standby mode. Once HPD_SINK
goes HIGH, the PTN3366 can operate and its behavior is controlled further by other
control pins — OE_N, DDC_EN.
The HPD channel operates independent of all these control signals.
HPD_SOURCE output follows the HPD_SINK input regardless of the power mode.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

PTN3366BSMP

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Buy PTN3366BSMP
Manufacturer:
NXP Semiconductors
Description:
Equalizers PTN3366BS/HVQFN32///REEL 13 Q2 DP
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