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PTN3366BSMP

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
PTN3366 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1.1 — 22 May 2015 13 of 26
NXP Semiconductors
PTN3366
Low power HDMI/DVI level shifter supporting 3 Gbit/s operation
8. Limiting values
[1] Human Body Model: ANSI/ESDA/JEDEC JDS-001-2012 (Revision of ANSI/ESDA/JEDEC JS-001-2011),
ESDA/JEDEC Joint standard for ESD sensitivity testing, Human Body Model - Component level;
Electrostatic Discharge Association, Rome, NY, USA; JEDEC Solid State Technology Association,
Arlington, VA, USA.
[2] Charged Device Model: JESD22-C101E December 2009 (Revision of JESD22-C101D, October 2008),
standard for ESD sensitivity testing, Charged Device Model - Component level; JEDEC Solid State
Technology Association, Arlington, VA, USA.
9. Recommended operating conditions
[1] Input signals to these pins must be AC-coupled.
[2] Operation without external reference resistor is possible but results in reduced output voltage swing
accuracy. For details, see Section 7.2
.
9.1 Current consumption
Table 7. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage 0.3 +4.6 V
V
I
input voltage 3.3 V CMOS inputs 0.3 V
DD
+0.5 V
5.0 V CMOS inputs 0.3 6.0 V
T
stg
storage temperature 65 +150 C
V
ESD
electrostatic discharge
voltage
HBM
[1]
- 8000 V
CDM
[2]
- 1000 V
Table 8. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
V
DD
supply voltage 3.0 3.3 3.6 V
V
I
input voltage 3.3 V CMOS inputs 0 - 3.6 V
5.0 V CMOS inputs 0 - 5.5 V
V
I(AV)
average input
voltage
IN_Dn+, IN_Dn inputs
[1]
-0 -V
R
ref(ext)
external reference
resistance
connected between pin
REXT (pin 4) and GND
[2]
-12.4 1% - k
T
amb
ambient temperature operating in free air 40 - +105 C
Table 9. Current consumption
Symbol Parameter Conditions Min Typ Max Unit
I
DD
supply current OE_N = LOW; Active mode - 22 - mA
OE_N = LOW; HPD_SINK = LOW;
Standby mode
-25-A
OE_N = HIGH,
HPD_SINK = don’t care and
DDC_EN = LOW;
Ultra low-power mode
--10A
PTN3366 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1.1 — 22 May 2015 14 of 26
NXP Semiconductors
PTN3366
Low power HDMI/DVI level shifter supporting 3 Gbit/s operation
10. Characteristics
10.1 Differential inputs
[1] UI (unit interval) = t
bit
(bit time).
[2] UI is determined by the display mode. Nominal bit rate ranges from 250 Mbit/s to 3 Gbit/s per lane.
[3] V
RX_DIFFp-p
= 2 V
RX_D+
V
RX_D
. Applies to IN_Dx signals.
[4] V
i(cm)M(AC)
= V
RX_D+
+V
RX_D
/2 V
RX(cm)
.
V
RX(cm)
= DC (avg) of V
RX_D+
+V
RX_D
/2.
[5] Differential inputs switch to a high-impedance state when OE_N is HIGH.
Table 10. Differential input characteristics for IN_Dx signals
Symbol Parameter Conditions Min Typ Max Unit
UI unit interval
[1]
nominal value at 3.0 Gbit/s
[2]
-333-ps
nominal value at 250 Mbit/s
[2]
-4000-ps
V
RX_DIFFp-p
differential input peak-to-peak voltage
[3]
0.15 - 1.2 V
t
RX_EYE
receiver eye time minimum eye width at IN_Dx
input pair
0.8--UI
V
i(cm)M(AC)
peak common-mode input voltage
(AC)
includes all frequencies
above 30 kHz
[4]
--100mV
Z
i
input impedance DC input impedance 40 50 60
V
RX(bias)
bias receiver voltage 1.0 1.8 1.95 V
Z
I(se)
single-ended input impedance inputs in high-Z state
[5]
100 - - k
RL
in
input return loss differential input; active mode
f=100MHz - 20 - dB
f=1.5GHz - 16 - dB
f=3.0GHz - 11 - dB
PTN3366 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1.1 — 22 May 2015 15 of 26
NXP Semiconductors
PTN3366
Low power HDMI/DVI level shifter supporting 3 Gbit/s operation
10.2 Differential outputs
The level shifter’s differential outputs are designed to meet HDMI version 1.4b and
DVI version 1.0 specifications.
[1] V
TT
is the DC termination voltage in the HDMI or DVI sink. V
TT
is nominally 3.3 V.
[2] The open-drain output pulls down from V
TT
.
[3] Swing down from TMDS termination voltage (3.3 V 10 %).
[4] This differential skew budget is in addition to the skew presented between IN_D+ and IN_D paired input pins.
[5] This lane-to-lane skew budget is in addition to skew between differential input pairs.
[6] Jitter budget for differential signals as they pass through the level shifter.
Table 11. Differential output characteristics for OUT_Dx signals
Symbol Parameter Conditions Min Typ Max Unit
V
OH(se)
single-ended HIGH-level
output voltage
[1]
V
TT
0.01 V
TT
V
TT
+0.01 V
V
OL(se)
single-ended LOW-level
output voltage
[2]
V
TT
0.60 V
TT
0.50 V
TT
0.40 V
V
O(se)
single-ended output
voltage variation
logic 1 and logic 0 state applied
respectively to differential inputs
IN_Dx; R
ref(ext)
connected;
see Table 8
[3]
400 500 600 mV
I
OZ
OFF-state output current single-ended - - 10 A
t
r
rise time 20 % to 80 % 75 - 150 ps
t
f
fall time 80 % to 20 % 75 - 150 ps
t
sk
skew time intra-pair
[4]
-15-ps
inter-pair
[5]
--250ps
t
jit(add)
added jitter time jitter contribution for TMDS
signaling at 3.4 Gbit/s;
PRBS7 pattern;
EQ0=LOW;EQ1=LOW;
refer to Figure 4
[6]
-13-ps
Fig 4. Setup for added jitter measurement
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P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

PTN3366BSMP

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NXP Semiconductors
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Equalizers PTN3366BS/HVQFN32///REEL 13 Q2 DP
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