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PTN3366BSMP

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
PTN3366 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1.1 — 22 May 2015 10 of 26
NXP Semiconductors
PTN3366
Low power HDMI/DVI level shifter supporting 3 Gbit/s operation
7.1.2 Output Enable function (OE_N)
When input OE_N is asserted (active LOW), the IN_Dx and OUT_Dx signals are fully
functional. Input termination resistors are enabled and the internal bias circuits are turned
on.
When OE_N is de-asserted (inactive HIGH), the OUT_Dx outputs are in a
high-impedance state. The IN_Dx input buffers are disabled and IN_Dx termination is
disabled. Power consumption is minimized.
Remark: OE_N signal level has no influence on the HPD_SINK input, HPD_SOURCE
output, or the SCL and SDA level shifters.
7.1.3 DDC channel enable function (DDC_EN)
The DDC_EN pin is active HIGH and can be used to isolate a badly behaved slave. When
DDC_EN is LOW, the DDC channel is turned off. The DDC_EN input should never
change state during an I
2
C-bus operation. Note that disabling DDC_EN during a bus
operation may hang the bus, while enabling DDC_EN during bus traffic would corrupt the
I
2
C-bus operation. Hence, DDC_EN should only be toggled while the bus is idle. The DDC
channel enable (DDC_EN) and TMDS output enable (OE_N) can be controlled
independent of each other.
7.1.4 Enable/disable truth table
[1] A LOW level on input DDC_EN disables only the DDC channel.
[2] OUT_Dx channels ‘enabled’ means outputs OUT_Dx toggling in accordance with IN_Dx differential input voltage switching.
[3] DDC channel ‘enabled’ means SDA_SINK is connected to SDA_SOURCE and SCL_SINK is connected to SCL_SOURCE.
[4] The HPD_SOURCE output logic state always follows the HPD_SINK input logic state.
Table 4. HPD_SINK, OE_N and DDC_EN enabling truth table
Inputs Channels Mode
HPD_SINK OE_N DDC_EN
[1]
IN_Dx OUT_Dx
[2]
DDC
[3]
HPD_SOURCE
[4]
LOW LOW LOW high-Z high-Z high-Z LOW Standby
LOW LOW HIGH high-Z high-Z high-Z LOW Standby
LOW HIGH LOW high-Z high-Z high-Z LOW Ultra low power
LOW HIGH HIGH high-Z high-Z high-Z LOW Standby
HIGH LOW LOW 50 termination
to V
RX(bias)
outputs are
enabled
high-Z HIGH Active;
DDC disabled
HIGH LOW HIGH 50 termination
to V
RX(bias)
outputs are
enabled
SDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE
HIGH Active;
DDC enabled
HIGH HIGH LOW high-Z high-Z high-Z HIGH Ultra low power
HIGH HIGH HIGH 50 termination
to V
RX(bias)
high-Z SDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE
HIGH Standby;
DDC enabled
PTN3366 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1.1 — 22 May 2015 11 of 26
NXP Semiconductors
PTN3366
Low power HDMI/DVI level shifter supporting 3 Gbit/s operation
7.2 Analog current reference
The REXT pin (pin 6) is an analog current sense port used to provide an accurate current
reference for the differential outputs OUT_Dx. For best output voltage swing accuracy,
use of a 12.4 k resistor (1 % tolerance) connected between this terminal and GND is
recommended.
If an external 12.4 k1 % resistor is not used, this pin can be connected to GND or V
DD
directly (0 ). In any of these cases, the output functions normally but at reduced
accuracy over voltage and temperature of the following parameters: output levels (V
OL
),
differential output voltage swing, and rise and fall time accuracy.
7.3 Equalizer
The PTN3366 supports four level equalization settings based on binary input pins EQ0
and EQ1.
7.4 Backdrive current protection
The PTN3366 is designed for backdrive protection on all sink-side TMDS outputs,
sink-side DDC I/Os and the HPD_SINK input. This supports user scenarios where the
display is connected and powered, but the PTN3366 is unpowered. In these cases, the
PTN3366 sinks no more than a negligible amount of leakage current, and blocks the
display (sink) termination network from driving the power supply of the PTN3366 or that of
the inactive DVI or HDMI source or back into the V
DD
power supply rail.
7.5 Squelch function
PTN3366 operates only when the input signal level is above certain minimum threshold
(as per V
RX_DIFFp-p
). If the input falls below that minimum threshold, the outputs are
squelched.
7.6 Active DDC buffer with rise time accelerator
The PTN3366 DDC channel, besides providing 3.3 V to 5 V level shifting, includes active
buffering and rise time acceleration for reliable DDC applications. While retaining all the
operating modes and features of the I
2
C-bus system during the level shifts, it permits
extension of the I
2
C-bus by providing bidirectional buffering for both the data (SDA) and
the clock (SCL) line as well as the rise time accelerator on the sink-side port (SCL_SINK
and SDA_SINK) enabling the bus to drive a load up to 1400 pF and 400 pF on the
source-side port (SCL_SOURCE and SCA_SOURCE). Using the PTN3366 for DVI or
HDMI level shifting enables the system designer to isolate bus capacitance to
meet/exceed HDMI DDC specification. The SDA and SCL pins are in high-impedance
when the PTN3366 is unpowered or when DDC_EN is LOW.
Table 5. Equalizer settings
Inputs Equalization for 3 Gbit/s
EQ1 EQ0
short to GND short to GND 0 dB
short to GND short to V
DD
2dB
short to V
DD
short to GND 4 dB
short to V
DD
short to V
DD
6dB
PTN3366 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1.1 — 22 May 2015 12 of 26
NXP Semiconductors
PTN3366
Low power HDMI/DVI level shifter supporting 3 Gbit/s operation
PTN3366 has rise time accelerators on the sink-side port (SCL_SINK and SDA_SINK)
only. During positive bus transitions on the sink-side port, a current source is switched on
to quickly slew the SCL_SINK and SDA_SINK lines HIGH once the 5 V DDC bus V
IL
threshold level of around 1.5 V is exceeded, and turns off as the 5 V DDC bus V
IH
threshold voltage of approximately 3.5 V is approached.
7.7 Power management
PTN3366 implements innovative power management scheme whereby it achieves very
low power consumption in both active and standby modes. Based on OE_N, DDC_EN,
HPD_SNK, the PTN3366 intelligently optimizes the power consumption and disables
outputs (OUT_Dx). Refer to Table 6
.
Table 6. Power management schemes
OE_N DDC_EN HPD_SINK Source output PTN3366 power mode
LOW HIGH HIGH source active Active mode; DDC active
LOW HIGH LOW high-Z Standby mode
HIGH LOW don’t care high-Z Ultra low-power mode
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

PTN3366BSMP

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Manufacturer:
NXP Semiconductors
Description:
Equalizers PTN3366BS/HVQFN32///REEL 13 Q2 DP
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