LTC6994-1/LTC6994-2
11
699412fb
operaTion
The LTC6994 is built around a master oscillator with a 1µs
minimum period. The oscillator is controlled by the SET
pin current (I
SET
) and voltage (V
SET
), with a 1µs/50kΩ
conversion factor that is accurate to ±1.7% under typical
conditions.
t
MASTER
=
1µs
50kΩ
•
V
SET
I
SET
A feedback loop maintains V
SET
at 1V ±30mV, leaving I
SET
as the primary means of controlling the input-to-output
delay. The simplest way to generate I
SET
is to connect a
resistor (R
SET
) between SET and GND, such that I
SET
=
V
SET
/R
SET
. The master oscillator equation reduces to:
t
MASTER
= 1µs •
R
SET
50kΩ
From this equation, it is clear that V
SET
drift will not affect
the input-to-output delay when using a single program
resistor (R
SET
). Error sources are limited to R
SET
toler-
ance and the inherent accuracy ∆t
DELAY
of the LTC6994.
R
SET
may range from 50k to 800k (equivalent to I
SET
between 1.25µA and 20µA).
When the input makes a transition that will be delayed
(as determined by the part version and POL bit setting),
the master oscillator is enabled to time the delay. When
the desired duration is reached, the output is allowed to
transition.
The LTC6994 also includes a programmable frequency
divider which can further divide the frequency by 1, 8, 64,
512, 4096, 2
15
, 2
18
or 2
21
. This extends the delay duration
by those same factors. The divider ratio N
DIV
is set by a
resistor divider attached to the DIV pin.
t
DELAY
=
N
DIV
50kΩ
•
V
SET
I
SET
• 1µs
With R
SET
in place of V
SET
/I
SET
the equation reduces to:
t
DELAY
=
N
DIV
• R
SET
50kΩ
• 1µs
DIVCODE
The DIV pin connects to an internal, V
+
referenced 4-bit A/D
converter that determines the DIVCODE value. DIVCODE
programs two settings on the LTC6994:
1. DIVCODE determines the frequency divider setting,
N
DIV
.
2. The DIVCODE MSB is the POL bit, and configures a
different polarity setting on the two versions.
a. LTC6994-1: POL selects rising or falling-edge delays.
POL = 0 will delay rising-edge transitions. POL = 1
will delay falling-edge transitions.
b. LTC6994-2: POL selects the output inversion.
POL = 1 inverts the output signal.
V
DIV
may be generated by a resistor divider between V+
and GND as shown in Figure 1.
699412 F01
LTC6994
V
+
DIV
GND
R1
R2
Figure 1. Simple Technique for Setting DIVCODE
Table 1 offers recommended 1% resistor values that ac-
curately produce the correct voltage division as well as the
corresponding N
DIV
and POL values for the recommended
resistor pairs. Other values may be used as long as:
1. The V
DIV
/V
+
ratio is accurate to ±1.5% (including resis-
tor tolerances and temperature effects)
2. The driving impedance (R1||R2) does not exceed 500kΩ.
