LTC6994-1/LTC6994-2
16
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applicaTions inForMaTion
Basic Operation
The simplest and most accurate method to program the
LTC6994 is to use a single resistor, R
SET
, between the SET
and GND pins. The design procedure is a 3-step process.
Alternatively, Linear Technology offers the easy-to-use
TimerBlox Designer tool to quickly design any LTC6994
based circuit. Download the free TimerBlox Designer
software at www.linear.com/timerblox.
Step 1: Select the LTC6994 Version and POL Bit
Setting.
Choose LTC6994-1 to delay one (rising or falling) input
transition. The POL bit then defines which edge is to be
delayed. POL = 0 delays rising edges. POL = 1 delays
falling edges.
Choose LTC6994-2 to delay rising and falling edges. Set
POL = 0 for normal operation, or POL = 1 to invert the
output.
Step 2: Select the N
DIV
Frequency Divider Value.
As explained earlier, the voltage on the DIV pin sets the
DIVCODE which determines both the POL bit and the
N
DIV
value. For a given delay time (t
DELAY
), N
DIV
should
be selected to be within the following range:
t
DELAY
16µs
≤N
DIV
≤
t
DELAY
1µs
(1)
To minimize supply current, choose the lowest N
DIV
value.
However, in some cases a higher value for N
DIV
will provide
better accuracy (see Electrical Characteristics).
Table 1 can also be used to select the appropriate N
DIV
values for the desired t
DELAY
.
With POL already chosen, this completes the selection of
DIVCODE. Use Table 1 to select the proper resistor divider
or V
DIV
/V
+
ratio to apply to the DIV pin.
Step 3: Calculate and Select R
SET
.
The final step is to calculate the correct value for R
SET
using the following equation:
R
SET
=
50k
1µs
•
t
DELAY
N
DIV
(2)
Select the standard resistor value closest to the calculated
value.
Example: Design a circuit to delay falling edges by
t
DELAY
= 100µs with minimum power consumption.
Step 1: Select the LTC6994 Version and POL Bit
Setting.
To delay negative transitions, choose the LTC6994-1 with
POL = 1.
Step 2: Select the N
DIV
Frequency Divider Value.
Choose an N
DIV
value that meets the requirements of
Equation (1), using t
DELAY
= 100µs:
6.25 ≤ N
DIV
≤ 100
Potential settings for N
DIV
include 8 and 64. N
DIV
= 8 is
the best choice, as it minimizes supply current by us-
ing a large R
SET
resistor. POL = 1 and N
DIV
= 8 requires
DIVCODE = 14. Using Table 1, choose R1 = 102k and R2
= 976k values to program DIVCODE = 14.
Step 3: Select R
SET
.
Calculate the correct value for R
SET
using Equation (2).
R
SET
=
50k
1µs
•
100µs
8
= 625k
Since 625k is not available as a standard 1% resistor,
substitute 619k if a –0.97% shift in t
DELAY
is acceptable.
Otherwise, select a parallel or series pair of resistors such
as 309k and 316k to attain a more precise resistance.
The completed design is shown in Figure 9.
Figure 9. 100µs Negative-Edge Delay
LTC6994-1
IN
GND
SET
OUT
V
+
DIV
R1
102k
0.1µF
DIVCODE = 14
699412 F09
2.25V TO 5.5V
R2
976k
R
SET
625k
