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LTC6994MPS6-1#TRMPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
LTC6994-1/LTC6994-2
13
699412fb
operaTion
Figure 3. Rising-Edge Delayed Timing Diagram (LTC6994-1, POL = 0)
Figure 4. Falling-Edge Delayed Timing Diagram (LTC6994-1, POL = 1)
Edge-Controlled Delay
The LTC6994 is a programmable delay or pulse qualifier.
It can perform noise filtering, which distinguishes it from
a delay line (which simply delays all input transitions).
When the voltage on the LTC6994 input pin (IN) transitions
low or high, the LTC6994 can delay the corresponding
output transition by any time from 1µs to 33.6 seconds.
LTC6994-1 Functionality
Figures 3 details the basic operation of the LTC6994-1 when
configured to delay rising edge transitions (POL = 0). A
rising edge on the IN pin initiates the timing. OUT remains
low for the duration of t
DELAY
. If IN stays high then OUT
will transition high after this time. If the input doesn’t
remain high long enough for OUT to transition high then
the timing will restart on each successive rising edge. In
this way, the LTC6994-1 can serve as a pulse qualifier,
filtering out noisy or short signals.
On a falling edge at the input, the output will follow im-
mediately (after a short propagation delay t
PD
).Note that
the output pulse width may be extremely short if IN falls
immediately after OUT rises.
Figure
4 details the operation of the LTC6994-1 when
configured to delay falling edges (POL = 1).
IN
OUT
t
DELAY
t
PD
t
PD
t
DELAY
t
DELAY
t
PD
699412 F03
t
WIDTH
t
PD
t
PD
t
PD
IN
OUT
t
DELAY
t
PD
t
DELAY
t
PD
t
PD
t
PD
t
PD
t
PD
t
WIDTH
t
DELAY
699412 F04
LTC6994-1/LTC6994-2
14
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operaTion
LTC6994-2 Functionality
Figures 5 details the basic operation of the LTC6994-2
when configured for noninverting operation (POL = 0). As
before, a rising edge on the IN pin initiates the timing and,
if IN remains high, OUT will transition high after t
DELAY
.
Unlike the LTC6994-1, falling edges are delayed in the same
way. When IN transitions low, OUT will follow after t
DELAY
.
If the input doesn’t remain high or low long enough for
OUT to follow, the timing will restart on the next transition.
Also unlike the LTC6994-1, the output pulse width can
never be less than t
DELAY
. Therefore, the LTC6994-2 can
generate pulses with a defined minimum width.
Figure 6 details the operation of the LTC6994-2 when the
output is inverted (POL = 1).
Figure 5. Both Edges Delayed Timing Diagram (LTC6994-2, POL = 0)
Figure 6. Both Edges Delayed (Inverting) Timing Diagram (LTC6994-2, POL = 1)
IN
OUT
t
DELAY
t
PD
t
PD
t
PD
t
WIDTH
t
PD
t
DELAY
t
PD
t
DELAY
t
DELAY
699412 F05
IN
OUT
t
DELAY
t
PD
t
PD
t
PD
t
PD
t
PD
t
WIDTH
t
DELAY
t
DELAY
t
DELAY
699412 F06
LTC6994-1/LTC6994-2
15
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operaTion
Changing DIVCODE After Start-Up
Following start-up, the A/D converter will continue
monitoring V
DIV
for changes. Changes to DIVCODE will
be recognized slowly, as the LTC6994 places a priority on
eliminating any “wandering” in the DIVCODE. The typical
delay depends on the difference between the old and
new DIVCODE settings and is proportional to the master
oscillator period.
t
DIVCODE
= 16 • (∆DIVCODE + 6) • t
MASTER
A change in DIVCODE will not be recognized until it is
stable, and will not pass through intermediate codes. A
digital filter is used to guarantee the DIVCODE has settled
to a new value before making changes to the output. How-
ever, if the delay timing is active during the transition, the
actual delay can take on a value between the two settings.
Start-Up Time
When power is first applied, the power-on reset (POR)
circuit will initiate the start-up time, t
START
. The OUT pin
is held low during this time and the IN pin has no control
over the output. The typical value for t
START
ranges from
0.5ms to 8ms depending on the master oscillator frequency
(independent of N
DIV
):
t
START(TYP)
= 500 • t
MASTER
During start-up, the DIV pin A/D converter must determine
the correct DIVCODE before the LTC6994 can respond
to an input. The start-up time may increase if the supply
or DIV pin voltages are not stable. For this reason, it is
recommended to minimize the capacitance on the DIV
pin so it will properly track V
+
. Less than 100pF will not
extend the start-up time.
At the end of t
START
the DIVCODE and IN pin settings are
recognized, and the state of the IN pin is transferred to the
output (without additional delay). If IN is high at the end of
t
START
, OUT will go high. Otherwise OUT will remain low.
The LTC6994-2 with POL = 1 is the exception because it
inverts the signal. At this point, the LTC6994 is ready to
respond to rising/falling edges on the input.
DIV
500mV/DIV
IN
2V/DIV
OUT
2V/DIV
LTC6994-1
V
+
= 3.3V
R
SET
= 200k
500µs/DIV
699412 F07a
512µs
256µs
4µs
Figure 7a. DIVCODE Change from 0 to 2
DIV
500mV/DIV
IN
2V/DIV
OUT
2V/DIV
LTC6994-1
V
+
= 3.3V
R
SET
= 200k
500µs/DIV
699412 F07b
256µs
4µs
512µs
Figure 7b. DIVCODE Change from 2 to 0
IN
V
+
OUT
t
START
(IN IGNORED)
t
PD
699412 F08
IF IN = 1 AT END OF t
START
*
IF IN = 0 AT END OF t
START
*
*LTC6994-2 WITH POL = 1 INVERTS THE OUTPUT
Figure 8. Start-Up Timing Diagram
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

LTC6994MPS6-1#TRMPBF

Mfr. #:
Buy LTC6994MPS6-1#TRMPBF
Manufacturer:
Analog Devices Inc.
Description:
Delay Lines / Timing Elements DELAY with Rising or Falling Edge Trigger
Lifecycle:
New from this manufacturer.
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