LTC6994-1/LTC6994-2
9
699412fb
pin FuncTions
(DCB/S6)
V
+
(Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This sup-
ply should be kept free from noise and ripple. It should be
bypassed directly to the GND pin with a 0.1µF capacitor.
DIV (Pin 2/Pin 4): Programmable Divider and Polarity
Input. The DIV pin voltage (V
DIV
) is internally converted
into a 4-bit result (DIVCODE). V
DIV
may be generated by
a resistor divider between V
+
and GND. Use 1% resistors
to ensure an accurate result. The DIV pin and resistors
should be shielded from the OUT pin or any other traces
that have fast edges. Limit the capacitance on the DIV pin
to less than 100pF so that V
DIV
settles quickly. The MSB
of DIVCODE (POL) selects the delay functionality. For the
LTC6994-1, POL = 0 will delay the rising transition and
POL = 1 will delay the falling transition. For the LTC6994-
2, both transitions are delayed so POL = 1 can be used
to invert the output.
SET (Pin 3/Pin 3): Delay Setting Input. The voltage on the
SET pin (V
SET
) is regulated to 1V above GND. The amount
of current sourced from the SET pin (I
SET
) programs the
master oscillator frequency. The I
SET
current range is
1.25µA to 20µ
A. The delayed output transition will be not
occur if I
SET
drops below approximately 500nA. Once I
SET
increases above 500nA the delayed edge will transition.
A resistor connected between SET and GND is the most
accurate way to set the delay. For best performance, use
a precision metal or thin film resistor of 0.5% or better
tolerance and 50ppm/°C or better temperature coefficient.
For lower accuracy applications an inexpensive 1% thick
film resistor may be used.
Limit the capacitance on the SET pin to less than 10pF
to minimize jitter and ensure stability. Capacitance less
than 100pF maintains the stability of the feedback circuit
regulating the V
SET
voltage.
IN (Pin 4/Pin 1): Logic Input. Depending on the version and
POL bit setting, rising or falling edges on IN will propagate
to OUT after a programmable delay. The LTC6994-1 will
delay only the rising or falling edge. The LTC6994-2 will
delay both edges.
GND (Pin 5/Pin 2): Ground. Tie to a low inductance ground
plane for best performance.
OUT (Pin 6/Pin 6): Output. The OUT pin swings from
GND to V
+
with an output resistance of approximately
30Ω. When driving an LED or other low impedance load
a series
output resistor
should be used to limit source/
sink current to 20mA.
699412 PF
LTC6994
IN
GND
SET
OUT
V
+
DIV
C1
0.1µF
R
SET
R2
R1
V
+
V
+
