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LTC6994MPS6-1#TRMPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
LTC6994-1/LTC6994-2
19
699412fb
Power Supply Current
The Electrical Characteristics table specifies the supply
current while the part is idle (waiting for an input transi-
tion). I
S(IDLE)
varies with the programmed t
DELAY
and the
supply voltage, as described by the equations in Table 2,
valid for both the LTC6994-1 and LTC6994-2.
Table 2. Approximate Idle Supply Current Equations
CONDITION TYPICAL I
S(IDLE)
N
DIV
≤ 64
V
+
• N
DIV
• 7pF + 4pF
( )
t
DELAY
+
V
+
500kΩ
+ 2.2 •I
SET
+ 50µA
N
DIV
≥ 512
V
+
•N
DIV
• 7pF
t
DELAY
+
V
+
500kΩ
+ 1.8 •I
SET
+ 50µA
When an input transition starts the delay timing circuity,
the instantaneous supply current increases to I
S(ACTIVE)
.
I
S(ACTIVE)
= I
S(IDLE)
+ ∆I
S(ACTIVE)
applicaTions inForMaTion
∆I
S(ACTIVE)
can be estimated using the equations in Table 3,
assuming a periodic input with frequency f
IN
. The equa-
tions assume the input pulse width is greater than t
DELAY
;
otherwise, the output will not transition (and the increase
in supply current will be less).
Table 3. Active Increase in Supply Current
CONDITION DEVICE TYPICAL ∆I
S(ACTIVE)
*
N
DIV
≤ 64
LTC6994-1 f
IN
• V
+
• (N
DIV
• 5pF + 18pF + C
LOAD
)
LTC6994-2 f
IN
• V
+
• (N
DIV
• 10pF + 22pF + C
LOAD
)
N
DIV
≥ 512 Either Version f
IN
• V
+
• C
LOAD
*Ignoring resistive loads (assumes R
LOAD
= ∞)
Figures 14 and 15 show how the supply current increases
from I
S(IDLE
) as the input frequency increases. At higher
N
DIV
settings, the increase in active current is smaller.
f
IN
• t
DELAY
“IDLE”
POWER SUPPLY CURRENT (µA)
150
200
250
0.8
699412 F14
100
50
0
0.2
0.4
0.6
1.0
÷1, R
SET
= 50k
÷8, R
SET
= 50k
÷1, R
SET
= 100k
÷1, R
SET
= 800k
V
+
= 3.3V
INPUT PULSE WIDTH = 1.1 • t
DELAY
C
LOAD
= 5pF
R
LOAD
= ∞
f
IN
• t
DELAY
“IDLE”
POWER SUPPLY CURRENT (µA)
150
200
250
0.4
699412 F15
100
50
0
0.1
0.2
0.3
0.5
÷1, R
SET
= 50k
÷8, R
SET
= 50k
÷1, R
SET
= 100k
÷1, R
SET
= 800k
V
+
= 3.3V
f
IN
< 1/(2 • t
DELAY
) TO ALLOW RISING AND
FALLING DELAYS TO REACH THE OUTPUT
C
LOAD
= 5pF
R
LOAD
= ∞
Figure 14. I
S(ACTIVE)
vs Input Frequency, LTC6994-1 Figure 15. I
S(ACTIVE)
vs Input Frequency, LTC6994-2
LTC6994-1/LTC6994-2
20
699412fb
699412 F16
LTC6994
IN
GND
SET
OUT
V
+
DIV
C1
0.1µF
R1
R2
R
SET
V
+
V
+
DIV
SET
OUT
GND
IN
C1R1
R2
V
+
R
SET
DCB PACKAGE
IN
GND
SET
OUT
V
+
DIV
R2
V
+
R
SET
TSOT-23 PACKAGE
R1
C1
applicaTions inForMaTion
Figure 16. Supply Bypassing and PCB Layout
Supply Bypassing and PCB Layout Guidelines
The LTC6994 is an accurate monostable multivibrator when
used in the appropriate manner. The part is simple to use
and by following a few rules, the expected performance is
easily achieved. Adequate supply bypassing and proper
PCB layout are important to ensure this.
Figure 16 shows example PCB layouts for both the SOT-23
and DCB packages using 0603 sized passive components.
The layouts assume a two layer board with a ground plane
layer beneath and around the LTC6994. These layouts are
a guide and need not be followed exactly.
1. Connect the bypass capacitor, C1, directly to the V
+
and
GND pins using a low inductance path. The connection
from C1 to the V
+
pin is easily done directly on the top
layer. For the DCB package, C1’s connection to GND is
also simply done on the top layer. For the SOT-23, OUT
can be routed through the C1 pads to allow a good C1
GND connection. If the PCB design rules do not allow
that, C1’s GND connection can be accomplished through
multiple vias to the ground plane. Multiple vias for both
the GND pin
connection to
the ground plane and the
C1 connection to the ground plane are recommended
to minimize the inductance. Capacitor C1 should be a
0.1µF ceramic capacitor.
2. Place all passive components on the top side of the
board. This minimizes trace inductance.
3. Place R
SET
as close as possible to the SET pin and make
a direct, short connection. The SET pin is a current sum-
ming node and currents injected into this pin directly
modulate the output delay. Having a short connection
minimizes the exposure to signal pickup.
4. Connect R
SET
directly to the GND pin. Using a long path
or vias to the ground plane will not have a significant
affect on accuracy, but a direct, short connection is
recommended and easy to apply.
5. Use a ground trace to shield the SET pin. This provides
another layer of protection from radiated signals.
6. Place R1 and R2 close to the DIV pin. A direct, short
connection to the DIV pin minimizes the external signal
coupling.
LTC6994-1/LTC6994-2
21
699412fb
Typical applicaTions
Delayed One-Shot
LTC6994-1
OUT
V
+
DIV
IN
GND
SET
604k
IN
OUT
5V
0.1µF
IN
699412 TA02
LTC6993-1
t
RISE
_
DELAY
= 50ms
DELAY
50ms
DELAY SHOT
SHOT
10ms
t
ONESHOT
= 10ms
OUT
V
+
DIV
TRIG
GND
SET
121k
5V
0.1µF
DELAYED PULSE OUT
1M
392k
Pulse Stretcher
LTC6994-1
OUT
V
+
DIV
IN
GND
SET
t
MIN
= 1ms
OUTPUT PULSE DURATION = t
PULSE
_
IN
+ 1ms
V
+
0.1µF
976k
699412 TA03
787k
OUTIN
IN
OUT
t
MIN
182k
t
MIN
LTC6994-2
OUT
V
+
DIV
IN
GND
SET
t = 100ms
OUTPUT GOES TO SAME FINAL LEVEL OF INPUT
AFTER STABLE FOR 100ms
V
+
STABLECHATTER
OR
STABLECHATTER
0.1µF
523k
699412 TA04
154k
OUT
V
+
1M
V
+OR
Switch/Relay Debouncer
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

LTC6994MPS6-1#TRMPBF

Mfr. #:
Buy LTC6994MPS6-1#TRMPBF
Manufacturer:
Analog Devices Inc.
Description:
Delay Lines / Timing Elements DELAY with Rising or Falling Edge Trigger
Lifecycle:
New from this manufacturer.
Delivery:
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