AD9201ARSZ Datasheet AD9201ARSZRL, AD9201ARSZ, AD9201ARS | P4-P6

–3–

REV. D

AD9201

Parameter Symbol Min Typ Max Units Condition

DYNAMIC PERFORMANCE (SE)

Signal-to-Noise and Distortion SINAD

f = 3.58 MHz 52.3 dB

Signal-to-Noise SNR

f = 3.58 MHz 55.5 dB

Total Harmonic Distortion THD

f = 3.58 MHz –55 dB

Spurious Free Dynamic Range SFDR

f = 3.58 MHz –58 dB

DIGITAL INPUTS

High Input Voltage V

2.4 V

Low Input Voltage V

0.3 V

DC Leakage Current I

±6 µA

Input Capacitance C

2pF

LOGIC OUTPUT (with DVDD = 3 V)

High Level Output Voltage

= 50 µA) V

2.88 V

Low Level Output Voltage

= 1.5 mA) V

0.095 V

LOGIC OUTPUT (with DVDD = 5 V)

High Level Output Voltage

= 50 µA) V

4.5 V

Low Level Output Voltage

= 1.5 mA) V

0.4 V

Data Valid Delay t

11 ns

MUX Select Delay t

7ns

Data Enable Delay t

13 ns C

= 20 pF. Output Level to

90% of Final Value

Data High-Z Delay t

DHZ

13 ns

CLOCKING

Clock Pulsewidth High t

22.5 ns

Clock Pulsewidth Low t

22.5 ns

Pipeline Latency 3.0 Cycles

NOTES

AIN differential 2 V p-p, REFT = 1.5 V, REFB = –0.5 V.

IMD referred to larger of two input signals.

SE is single ended input, REFT = 1.5 V, REFB = –0.5 V.

Specifications subject to change without notice.

CLOCK

INPUT

SELECT

INPUT

DATA

OUTPUT

ADC SAMPLE

Q CHANNEL

OUTPUT ENABLED

I CHANNEL

OUTPUT ENABLED

SAMPLE #1-3

Q CHANNEL

OUTPUT

SAMPLE #1-2

Q CHANNEL

OUTPUT

SAMPLE #1-1

Q CHANNEL

OUTPUT

SAMPLE #1-1

I CHANNEL

OUTPUT

SAMPLE #1

Q CHANNEL

OUTPUT

SAMPLE #1

I CHANNEL

OUTPUT

SAMPLE #2

Q CHANNEL

OUTPUT

Figure 1. ADC Timing

AD9201

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REV. D

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD9201 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

ABSOLUTE MAXIMUM RATINGS*

With

Respect

Parameter to Min Max Units

AVDD AVSS –0.3 +6.5 V

DVDD DVSS –0.3 +6.5 V

AVSS DVSS –0.3 +0.3 V

AVDD DVDD –6.5 +6.5 V

CLK AVSS –0.3 AVDD + 0.3 V

Digital Outputs DVSS –0.3 DVDD + 0.3 V

AINA, AINB AVSS –1.0 AVDD + 0.3 V

VREF AVSS –0.3 AVDD + 0.3 V

REFSENSE AVSS –0.3 AVDD + 0.3 V

REFT, REFB AVSS –0.3 AVDD + 0.3 V

Junction Temperature +150 °C

Storage Temperature –65 +150 °C

Lead Temperature

10 sec +300 °C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum ratings

for extended periods may effect device reliability.

ORDERING GUIDE

Temperature Package Package

Model Range Description Options*

AD9201ARS –40°C to +85°C 28-Lead SSOP RS-28

AD9201-EVAL Evaluation Board

*RS = Shrink Small Outline.

PIN CONFIGURATION

TOP VIEW

(Not to Scale)

AD9201

REFT-Q

INB-Q

INA-Q

CHIP-SELECT

VREF

AVDD

REFB-Q

REFB-I

AVSS

REFSENSE

REFT-I

SLEEP

INA-I

INB-I

DVSS

DVDD

(LSB) D0

(MSB) D9

SELECT

CLOCK

PIN FUNCTION DESCRIPTIONS

No. Name Description

1 DVSS Digital Ground

2 DVDD Digital Supply

3 D0 Bit 0 (LSB)

4 D1 Bit 1

5 D2 Bit 2

6 D3 Bit 3

7 D4 Bit 4

8 D5 Bit 5

9 D6 Bit 6

10 D7 Bit 7

11 D8 Bit 8

12 D9 Bit 9 (MSB)

13 SELECT Hi I Channel Out, Lo Q Channel Out

14 CLOCK Clock

15 SLEEP Hi Power Down, Lo Normal Operation

16 INA-I I Channel, A Input

17 INB-I I Channel, B Input

18 REFT-I Top Reference Decoupling, I Channel

19 REFB-I Bottom Reference Decoupling, I Channel

20 AVSS Analog Ground

21 REFSENSE Reference Select

22 VREF Internal Reference Output

23 AVDD Analog Supply

24 REFB-Q Bottom Reference Decoupling, Q Channel

25 REFT-Q Top Reference Decoupling, Q Channel

26 INB-Q Q Channel, B Input

27 INA-Q Q Channel, A Input

28 CHIP-SELECT Hi-High Impedance, Lo-Normal Operation

WARNING!

ESD SENSITIVE DEVICE

DEFINITIONS OF SPECIFICATIONS

INTEGRAL NONLINEARITY (INL)

Integral nonlinearity refers to the deviation of each individual

code from a line drawn from “zero” through “full scale.” The

point used as “zero” occurs 1/2 LSB before the first code tran-

sition. “Full scale” is defined as a level 1 1/2 LSBs beyond the

last code transition. The deviation is measured from the center

of each particular code to the true straight line.

DIFFERENTIAL NONLINEARITY (DNL, NO MISSING

CODES)

An ideal ADC exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. It is often

specified in terms of the resolution for which no missing codes

(NMC) are guaranteed.

AD9201

–5–

REV. D

scale. Gain error is the deviation of the actual difference be-

tween first and last code transitions and the ideal difference

between the first and last code transitions.

GAIN MATCH

The change in gain error between I and Q channels.

PIPELINE DELAY (LATENCY)

The number of clock cycles between conversion initiation and

the associated output data being made available. New output

data is provided every rising clock edge.

MUX SELECT DELAY

The delay between the change in SELECT pin data level and

valid data on output pins.

POWER SUPPLY REJECTION

The specification shows the maximum change in full scale from

the value with the supply at the minimum limit to the value with

the supply at its maximum limit.

APERTURE JITTER

Aperture jitter is the variation in aperture delay for successive

samples and is manifested as noise on the input to the A/D.

APERTURE DELAY

Aperture delay is a measure of the Sample-and-Hold Amplifier

(SHA) performance and is measured from the rising edge of the

clock input to when the input signal is held for conversion.

SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)

RATIO

S/N+D is the ratio of the rms value of the measured input signal

to the rms sum of all other spectral components below the

Nyquist frequency, including harmonics but excluding dc.

The value for S/N+D is expressed in decibels.

DRVDD

AVSS

DRVSS

AVDD

AVSS

AVDD

REFBS

REFBF

AVDD

AVSS

AVDD

AVSS

AVDD

AVSS

AVDD

AVSS

AVDD

AVSS

AVDD

AVSS

AVDD

AVSS

d. INA, INB e. Reference f. REFSENSE g. VREF

Figure 2. Equivalent Circuits

a. D0–D9, OTR b. Three-State, Standby c. CLK

OFFSET ERROR

The first transition should occur at a level 1 LSB above “zero.”

Offset is defined as the deviation of the actual first code transi-

tion from that point.

OFFSET MATCH

The change in offset error between I and Q channels.

EFFECTIVE NUMBER OF BITS (ENOB)

For a sine wave, SINAD can be expressed in terms of the num-

ber of bits. Using the following formula,

N = (SINAD – 1.76)/6.02

It is possible to get a measure of performance expressed as N,

the effective number of bits.

Thus, effective number of bits for a device for sine wave inputs

at a given input frequency can be calculated directly from its

measured SINAD.

TOTAL HARMONIC DISTORTION (THD)

THD is the ratio of the rms sum of the first six harmonic com-

ponents to the rms value of the measured input signal and

is expressed as a percentage or in decibels.

SIGNAL-TO-NOISE RATIO (SNR)

SNR is the ratio of the rms value of the measured input signal to

the rms sum of all other spectral components below the Nyquist

frequency, excluding the first six harmonics and dc. The value

for SNR is expressed in decibels.

SPURIOUS FREE DYNAMIC RANGE (SFDR)

The difference in dB between the rms amplitude of the input

signal and the peak spurious signal.

GAIN ERROR

The first code transition should occur for an analog value 1 LSB

above nominal negative full scale. The last transition should

occur for an analog value 1 LSB below the nominal positive full

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

AD9201ARSZ

Mfr. #:

Buy AD9201ARSZ

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC Dual CH 20MHz 10B Resolution CMOS

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AD9201ARSZ

AD9201ARSZ

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