NCP4326
http://onsemi.com
18
Detailed Regulation Principle
At the beginning of the Ton period the capacitor
connected on Ct pin is discharged and the internal current
source is shunted to V
CT_min
(1.6 V) via the bipolar
transistor until the end of the Ton period.
The internal current source starts to charge the capacitor
connected on Ct pin at the beginning of the Toff period. As
long as the voltage on the Ct pin is below the CPX pin, the
secondary switch is kept ON (i.e.: The secondary switch is
turned ON at the beginning of the primary on−time). By this
method the secondary power MOSFET can only be
switched ON one time per Toff period and prevents from any
hysteretic switching to the secondary side. The secondary
switch is synchronized with the primary switching
frequency, the secondary controller sets only the duty cycle.
The Ct capacitor value determines only the voltage swing
present at the Ct pin, which it used to generate the secondary
duty cycle.
The secondary regulation is working in trailing edge mode
control. The trailing edge mode control has been preferred
for its superior cross load performance.
The following picture (Figure 40) shows only one output
regulation, but the second output regulation works similarly
and independently from the other one. Nevertheless, both
regulations use the same synchronization signal:
• Beginning of ON time period (switch ON of the
secondary mosfet)
• The same ramp on Ct pin for adjusting in respect to the
error amplifier level the secondary duty−cycle to the
both outputs drives.
Figure 40. Detailed Principle Regulation
Toff
Ton
Switch
ON
Switch
OFF
Primary Drain
Voltage (200 V/div)
DRV1 pin signal
(10 V/div)
Ct ramp (2 V/div)
Error amplifier
output voltage (CP1
pin) (2 V/div)
