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NCP4326DR2

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NCP4326
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28
The operational amplifier is an open collector type that it
allows to sink the current from the opto−coupler from any
voltage source level.
Figure 53 illustrates an example of a close loop feedback
connection from the secondary and the primary side.
1V25
FBm
CPm
8
GND
9
Rup
Rdown
GND
U5
Opto
R33
1k
CFB_compRFB_comp
D1
C1
GND
L1
C2
Prim FB
NCP4326
VOut
Q1
Primary
Controller
Figure 53. Primary Feedback Connection
−
+
+
+
V
DD1
V
CC
Components Determination
RC Network on Flux Pin
The flux image can be obtained with a negative output or
with a forward configuration. The winding voltage
integration yields the flux image inside the transformer. This
integration will be done with a basic integrator.
The time constant of this integrator should be significantly
large compare to the maximum primary switching period.
For example the time constant can be 5−10 times larger.
Thus the resistor acts like a constant current source during
the period, so that the voltage across the capacitor rises and
falls linearly.
The internal flux signal (Int_Flux, see Figure 46) is
clamped to 4.5 volts in order to ensure a proper disable
soft−start function when the enable pin voltage is at its
maximum value (5.0 V).
For achieving a proper soft−start without any action from
the 4.5 V internal clamp, the maximum input voltage on flux
pin must be lower or equal to:
V
clamp
* V
offset
OpAmp_gain
that yields
4.5 * 0.5
10
+ 0.4 V.
So Vflux_pin should be lower or equal to 400 mV when
the power supply is in full load condition and at low line
input voltage.
Practically in case of universal input voltage range and
with a maximum output power to 16 W, a 10 nF capacitor is
selected and the resistor is adjusted to guaranteed a
maximum voltage on the flux to 400 mV at low line input
voltage. This gives a 22 k resistor.
Ct Capacitor
This capacitor is used to create the saw tooth for achieving
the pulse width modulation (PWM) for the both secondary
outputs regulated by the NCP4326.
The capacitor value can be determined with the following
equation:
I + C
V
t
´ C + I
t
V
, where I = I
Ct
, ΔV =
(V
CT_max1
−V
CT_min
), Δt = primary off time (time during the
capacitor is charged).
The capacitor value is calculated in the worst condition:
• I = I
Ctmax
= 700 A
• ΔV = (V
CT_max1
−V
CT_min
) = 4.0 − 1.6 = 2.4 V
• Δt = maximum primary off time in worst case condition
(Full load and low line input).
NCP4326
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29
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
18
16 9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B
S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A
S
T
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
____
NCP4326
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30
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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PUBLICATION ORDERING INFORMATION
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Phone: 81−3−5773−3850
NCP4326/D
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NCP4326DR2

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