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In a startup sequence, the voltage output is null so the error
amplifier output is at its max value, so the duty cycle from
the PWM_reg signal is at 100% duty cycle. The duty cycle
is only limited by the soft−start feature: the switch ON is
done when the Int_Flux voltage is become lower than the
enable pin voltage and the switch OFF is done when the
Int_Flux is become higher than the enable pin voltage.
The following Figure 48 show a real soft−start on a typical
application. The limited peak current during the soft−start
allows selecting smaller mosfet (for example SOT23
package without risk of exceeding the max non repetitive
peak current “IDM”).
1V8 output voltage
(0.5V/div)
Output peak current
in the power mosfet
(2A/div)
Soft start mode
on 1V8 output
Mixed Mode
Steady state
Normal reg.
Figure 48. Startup Sequence with Soft−Start on 1V8 Output at Full Load
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Standby Pin Feature Description
The standby pin enables or disables the controller in order
to save some power when the power supply is in standby
mode. In standby mode all the internal power supplies and
references are shut down, except the V
DD1
and the voltage
reference connected to the shunt regulator. The shunt
regulator bloc works during the standby mode for supplying
the feedback to the primary controller.
When the standby pin is released the both drivers are kept
in OFF state during T
stby_off
time to prevent any parasitic
switches on the driver before the internal power ON of the
controller is fully finished.
Practically the internal standby signal for the driver is
delayed and in the mean time the internal power waking up
is done.
DRV1
VOLTAGE
REFERENCE
GND
STBY
Vcc OK
Vcc OK
1V25
GND
2V5
+
2V5
SoftStart
STBY
DELAY
Figure 49. Standby Delay Definition
V
CC
V
CC
V
CC
UVLO
V
CC
V
DD1
V
DD1
V
DD
V
DD1
*V
DD
is not available in standby mode
**V
DD1
is available all the time
Synchronization Pin
The NCP4326 needs to be synchronized with the primary
controller, a dedicated pin ensures this function just by
sensing a secondary winding voltage and filtering it.
The RC network (Rsync1 and Csync) filters the secondary
winding and Rsync2 limits the current through the internal
zener diode when the voltage exceeds the zener clamp level
or when the zener conduct in forward mode (when the
voltage winding is negative).
+
GND
Sync
Ct
ICt
GND
Enable
4V01V6
GND
GND
Ct
Csync
Rsync1 Rsync2
GND
Flyback transformer
D1
Mag
GND
NCP4326
Figure 50. Synchronization Pin Wiring
V
DD
V
DD
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Secondary winding
voltage (20V/div)
Sync pin voltage
(5V/div).
Ct pin voltage
(2V/div)
Figure 51. Soft−Start Duty Cycle Generation During the Startup Sequence.
During the primary on time, the secondary winding
voltage is equal to the input voltage multiplied by the
transformer turn ratio. At the primary switch on or the falling
edge on the secondary winding voltage, the Ct capacitor
voltage is reset to VCt_min and keeps it to this value as long
as the primary switch is in ON state. Then when the primary
ON time ends the Ct capacitor voltage is released, thus with
the internal current source on Ct pin, the voltage capacitor
rises linearly until a new primary switching cycle.
Primary Feedback Regulation
The NCP4326 integrates a precision reference voltage,
which together with a dedicated operational amplifier
reduces the feedback loop elements to the minimum. This
error operational amplifier with the reference voltage has
called the shunt regulator and offers the same behavior of a
traditional TL431 or TLV431.
1V25
FBm
CPm
8
+
GND
9
NCP4326
FBm
CPm
8
9
GND
TLV431
Figure 52. Equivalent Schematic of the Shunt Regulator
V
DD1

NCP4326DR2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC REG SECONDARY CTR 3OUT 16SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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