IR3502BMTRPBF Datasheet IR3502BMTRPBF | P13-P15

IR3502B

Page 13 of 38 V3.2

IR3502B THEORY OF OPERATION

Block Diagram

The block diagram of the IR3502B is shown in Figure 7.

VID Control

The control IC allows the processor voltage to be set by a parallel eight bit digital VID bus. The VID codes set the

VDAC as shown in Table 1. The VID pins require an external bias voltage and should not be floated. The VID input

comparators monitor the VID pins and control the Digital-to-Analog Converter (DAC), whose output is sent to the

VDAC buffer amplifier. The output of the buffer amplifier is the VDAC pin. The VDAC voltage, input offsets of error

amplifier and remote sense differential amplifier are post-package trimmed to achieve 0.5% system set-point accuracy

for VID range between 1V to 1.6V. A set-point accuracy of ±5mV and ±8mV is achieved for VID ranges of 0.8V-1V and

0.5V-0.8V respectively. The actual VDAC voltage does not determine the system accuracy, which has a wider

tolerance.

The IR3502B can accept changes in the VID code while operating and vary the VDAC voltage accordingly. The slew

rate of the voltage at the VDAC pin can be adjusted by an external capacitor between VDAC pin and LGND pin. A

resistor connected in series with this capacitor is required to compensate the VDAC buffer amplifier. Digital VID

transitions result in a smooth analog transition of the VDAC voltage and converter output voltage minimizing inrush

currents in the input and output capacitors and overshoot of the output voltage.

Adaptive Voltage Positioning

Adaptive voltage positioning is needed to optimize the output voltage deviations during load transients and the power

dissipation of the load at heavy load. The circuitry related to voltage positioning is shown in Figure 8. The output

voltage is set by the reference voltage VSETPT at the positive input to the error amplifier. This reference voltage can

be programmed to have a constant DC offset below the VDAC by connecting RSETPT between VDAC and VSETPT.

The IVSETPT is controlled by the ROSC.

The average load current information for all the phases is fed back to the control IC through the IIN pin. As shown in

Figure 8, this information is thermally compensated with some gain by a set of buffer and thermal compensation

amplifiers to generate the voltage at the VDRP pin. The VDRP pin is connected to the FB pin through the resistor

DRP. Since the error amplifier will force the loop to maintain FB to be equal to the VDAC reference voltage, an

additional current will flow into the FB pin equal to (VDRP-VDAC) / R

DRP. When the load current increases, the VDRP

voltage increases accordingly. More current flows through the feedback resistor R

FB and causes the output to have

more droop. The positioning voltage can be programmed by the resistor R

DRP so that the droop impedance produces

the desired converter output impedance. The offset and slope of the converter output impedance are referenced to and

therefore independent of the VDAC voltage.

Inductor DCR Temperature Compensation

A negative temperature coefficient (NTC) thermistor should be used for inductor DCR temperature compensation. The

thermistor and tuning resistor network connected between the VN and VDRP pins provides a single NTC thermal

compensation. The thermistor should be placed close to the power stage to accurately reflect the thermal performance of

the inductor DCR. The resistor in series with the thermistor is used to reduce the nonlinearity of the thermistor.

Remote Voltage Sensing

VOSEN+ and VOSEN- are used for remote sensing and connected directly to the load. The remote sense differential

amplifier with high speed, low input offset and low input bias current ensures accurate voltage sensing and fast

transient response. There is finite input current at both pins VOSEN+ and VOSEN- due to the internal resistor of the

differential amplifier. This limits the size of the resistors that can be used in series with these pins for acceptable

regulation of the output voltage.

IR3502B

Page 14 of 38 V3.2

400K

CURRENT

REPORT AMP

VDRP

THERMAL COMP

VDAC

BUFFER AMP

DAC_BUFF

VDRP

200K

DAC_BUF

100K

200K

IMON

VCCL

200K

IROSC

VOSEN-

DISABLE

VCCL UVLO

R Q

VID FAULT

FAULT LATCH1

VDAC

VCCL UVLO

VID FAULT LATCH

FAULT LATCH2

1.17V

OV FAULT

OV@OPERATION

OV@START

VCCL UVLO

RESET

OV@START

OC after VRRDY

VCCL UVLO

SS RESET

OPEN SENSE LINE

VCCL UVLO

OPEN DAISY CHAIN

OC before VRRDY

OV FAULT

EAOUT

SS RESET

OPEN VOLTAGE LOOP

VCCL

25k

R Q

25k

VID2

VID4

VID3

VID7

VID6

PGOOD

SS/DEL

VID5

PHSOUT

CLKOUT

VID0

VID1

ENABLE

VCCLDRV

VRHOT

HOTSET

VCCL

PHSIN

EAOUT

VDAC

VOSEN-

VOSEN+

IIN

VSETPT

DAC_BUF

VCCLVCCL

VID4

VID5

VID6

VID7

VID1

VID2

VID3

1.03

VID6

VID7

VID0

VID2

VID3

VID4

VID5

PHSIN

VBOOT

VID0

VID1 VIDSEL

VIDSEL

PHSOUT

IROSC

DISABLE

IVOSEN-VIDSEL

PHSOUT

CLKOUT

FAULT

IROSC

F_VDAC

VID0

DIS

SS CLEARED

FAULT LATCH1

VID INPUT

COMPARATORS

(1/8 SHOWN)

SS RESET

ERROR

AMPLIFIER

DELAY

COMPARATOR

SET

DOMINANT

4.0V

800mV

ENABLE

COMPARATOR

DIGITAL

TO ANALOG

CONVERTER

1.3uS

BLANKING

850mV

VBOOT

(1.1V)

VDAC BUFFER

AMPLIFIER

INTERNAL

VDAC

VDRP

DAC_BUF

SET

DOMINANT

VBOOT

LATCH

VCCL REGULATOR

AMPLIFIER

OVER

VOLTAGE

COMPARATOR

VID SAMPLE

DELAY

COMPARATOR

250nS

BLANKING

VDRP

VCCL OUTPUT

COMPARATOR

ISOURCE

REMOTE SENSE

AMPLIFIER

6.8V

VRHOT COMPARATOR

CURRENT

SOURCE

GENERATOR

OC DELAY

COUNTER

RESET

DOMINANT

POWER OK

LATCH

ISINK

VID FAULT

LATCH

INTEL

0.2V

DISCHARGE

COMPARATOR

80mV

120mV

1.6V

50mV

DYNAMIC

VID

FAULT

SET

DOMINANT

IVOSEN-IVOSEN+

200mV

1.21V

POWER-UP OV

COMPARATOR

0.4V

DYNAMIC VID DETECT

COMPARATOR

6.1V

SOFT

START

CLAMP

ISETPT

UV CLEARED

FAULT LATCH2

SET

DOMINANT

OC LIMIT

COMPARATOR

1.4V

OPEN SENSE

LINE DETECT

COMPARATORS

60mV

130mV

3mV

4.5uA

OPEN SENSE LINE

0.6V

OPEN DAISY

CHAIN

VCCLDRV-0.2V

OC LIMIT

AMPLIFIER

IDCHG

OPEN SENSE

LINE DETECT

COMPARATORS

DETECTION

PULSE

DETECTION

PULSE

8-Pulse

Delay

1.08V

SET

DOMINANT

OV FAULT

LATCH

1.6V

1.5V

OV@OPERATION

ROSC/OVP

0.6V

LGND

ROSC BUFFER

AMPLIFIER

VCCLDRV

OV@START

VDAC

VCCLDRV

6.45V

5.45V

315mV

275mV

OV FAULT

Hold

Last VID

FAULT LATCH1

FAULT LATCH2

Figure 7 Block Diagram

IR3502B

Page 15 of 38 V3.2

TABLE 1 VR11 VID TABLE (PART1)

Hex (VID7:VID0) Dec (VID7:VID0) Voltage Hex (VID7:VID0) Dec (VID7:VID0) Voltage

00 00000000 Fault 40 01000000 1.21250

01 00000001 Fault 41 01000001 1.20625

02 00000010 1.60000 42 01000010 1.20000

03 00000011 1.59375 43 01000011 1.19375

04 00000100 1.58750 44 01000100 1.18750

05 00000101 1.58125 45 01000101 1.18125

06 00000110 1.57500 46 01000110 1.17500

07 00000111 1.56875 47 01000111 1.16875

08 00001000 1.56250 48 01001000 1.16250

09 00001001 1.55625 49 01001001 1.15625

0A 00001010 1.55000 4A 01001010 1.15000

0B 00001011 1.54375 4B 01001011 1.14375

0C 00001100 1.53750 4C 01001100 1.13750

0D 00001101 1.53125 4D 01001101 1.13125

0E 00001110 1.52500 4E 01001110 1.12500

0F 00001111 1.51875 4F 01001111 1.11875

10 00010000 1.51250 50 01010000 1.11250

11 00010001 1.50625 51 01010001 1.10625

12 00010010 1.50000 52 01010010 1.10000

13 00010011 1.49375 53 01010011 1.09375

14 00010100 1.48750 54 01010100 1.08750

15 00010101 1.48125 55 01010101 1.08125

16 00010110 1.47500 56 01010110 1.07500

17 00010111 1.46875 57 01010111 1.06875

18 00011000 1.46250 58 01011000 1.06250

19 00011001 1.45625 59 01011001 1.05625

1A 00011010 1.45000 5A 01011010 1.05000

1B 00011011 1.44375 5B 01011011 1.04375

1C 00011100 1.43750 5C 01011100 1.03750

1D 00011101 1.43125 5D 01011101 1.03125

1E 00011110 1.42500 5E 01011110 1.02500

1F 00011111 1.41875 5F 01011111 1.01875

20 00100000 1.41250 60 01100000 1.01250

21 00100001 1.40625 61 01100001 1.00625

22 00100010 1.40000 62 01100010 1.00000

23 00100011 1.39375 63 01100011 0.99375

24 00100100 1.38750 64 01100100 0.98750

25 00100101 1.38125 65 01100101 0.98125

26 00100110 1.37500 66 01100110 0.97500

27 00100111 1.36875 67 01100111 0.96875

28 00101000 1.36250 68 01101000 0.96250

29 00101001 1.35625 69 01101001 0.95625

2A 00101010 1.35000 6A 01101010 0.95000

2B 00101011 1.34375 6B 01101011 0.94375

2C 00101100 1.33750 6C 01101100 0.93750

2D 00101101 1.33125 6D 01101101 0.93125

2E 00101110 1.32500 6E 01101110 0.92500

2F 00101111 1.31875 6F 01101111 0.91875

30 00110000 1.31250 70 01110000 0.91250

31 00110001 1.30625 71 01110001 0.90625

32 00110010 1.30000 72 01110010 0.90000

33 00110011 1.29375 73 01110011 0.89375

34 00110100 1.28750 74 01110100 0.88750

35 00110101 1.28125 75 01110101 0.88125

36 00110110 1.27500 76 01110110 0.87500

37 00110111 1.26875 77 01110111 0.86875

38 00111000 1.26250 78 01111000 0.86250

39 00111001 1.25625 79 01111001 0.85625

3A 00111010 1.25000 7A 01111010 0.85000

3B 00111011 1.24375 7B 01111011 0.84375

3C 00111100 1.23750 7C 01111100 0.83750

3D 00111101 1.23125 7D 01111101 0.83125

3E 00111110 1.22500 7E 01111110 0.82500

3F 00111111 1.21875 7F 01111111 0.81875

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IR3502BMTRPBF

Mfr. #:

Buy IR3502BMTRPBF

Manufacturer:

Infineon Technologies

Description:

Power Management Specialized - PMIC X-PHASE CONTROL IC AMD SVID CTRL IC

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IR3502BMTRPBF