IR3502B
Page 20 of 38 V3.2
start to occur. If an over-current condition is again encountered during the soft start cycle, the over-current action
will repeat and the converter will be in hiccup mode.
Linear Regulator Output (VCCL)
The IR3502B has a built-in linear regulator controller, and only an external NPN transistor is needed to create a
linear regulator. The voltage of VCCL is fixed at 6.8V with the feedback resistive divider internal to the IC. The
regulator output powers the gate drivers of the phase ICs and circuits in the control IC, and the voltage is usually
programmed to optimize the converter efficiency. The linear regulator can be compensated by a 4.7uF capacitor at
the VCCL pin. As with any linear regulator, due to stability reasons, there is an upper limit to the maximum value of
capacitor that can be used at this pin and it’s a function of the number of phases used in the multiphase architecture
and their switching frequency. Figure 12 shows the stability plots for the linear regulator with 5 phases switching at
750 kHz.
VCCL Under Voltage Lockout (UVLO)
The IR3502B has no under voltage lockout for converter input voltage (VCC), but monitors the VCCL voltage
instead, which is used for the gate drivers of phase ICs and circuits in control IC and phase ICs. During power up,
the fault latch will be reset if VCCL is above 94% of 6.8V. If VCCL voltage drops below 80% of 6.8V, the fault latch
will be set.
Figure 12 VCCL regulator stability with 5 phases and PHSOUT equals 750 kHz.
Over Voltage Protection (OVP)
Output over-voltage happens during normal operation if a high side MOSFET short occurs or if output voltage is out of
regulation. The over-voltage protection comparator monitors VO pin voltage. If VO pin voltage exceeds VDAC by
130mV after SS, as shown in Figure 13, IR3502B raises ROSC/OVP pin voltage above to V(VCCL) - 1V, which sends
over voltage signal to system. During startup, the threshold is 130 mV above last VID and reverts back to
VBOOT+130mV during boot mode. The ROSC/OVP pin can also be connected to a thyrister in a crowbar circuit,
which pulls the converter input low in over voltage conditions. The over voltage condition also sets the over voltage
fault latch, which pulls error amplifier output low to turn off the converter output. At the same time IIN pin (IIN of phase
ICs) is pulled up to VCCL to communicate the over voltage condition to phase ICs, as shown in Figure 13. In each
phase IC, the OVP circuit overrides the normal PWM operation and will fully turn-on the low side MOSFET within
approximately 150ns. The low side MOSFET will remain on until IIN pin voltage drops below V(VCCL) - 800mV, which
signals the end of over voltage condition. An over voltage fault condition is latched in the IR3502B and can only be
cleared by cycling power to the IR3502B VCCL.
