IR3502B
Page 34 of 38 V3.2
LAYOUT GUIDELINES
The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB
layout, therefore minimizing the noise coupled to the IC.
Dedicate at least one middle layer for a ground plane LGND.
Connect the ground tab under the control IC to LGND plane through a via.
Place VCCL decoupling capacitor VCCL as close as possible to VCCL and LGND pins.
Place the following critical components on the same layer as control IC and position them as close as possible
to the respective pins, R
OSC, RVDAC, CVDAC, and CSS/DEL. Avoid using any via for the connection.
Place the compensation components on the same layer as control IC and position them as close as possible to
EAOUT, FB, VO and VDRP pins. Avoid using any via for the connection.
Use Kelvin connections for the remote voltage sense signals, VOSNS+ and VOSNS-, and avoid crossing over
the fast transition nodes, i.e. switching nodes, gate drive signals and bootstrap nodes.
Avoid analog control bus signals, VDAC, IIN, and especially EAOUT, crossing over the fast transition nodes.
Separate digital bus, CLKOUT, PHSOUT and PHSIN from the analog control bus and other compensation
components.
HOTSETVCCLDRV
PGOOD
IMON ENABLE
VOSNS –
To
Phase ICs
Digital
To VCCL
GND
SS/DEL
VDAC
IIN
VRHOT
VSETPT VID3
VID4
ROSC
VID5
VID6
VID7
VCCL
tcmp3
PHSOUT
CLKOUT
PHSIN
VID2
VID1
VID0
mon
mon
vccl2
To SYSTEM
cp1
Rhotset2
Rhotset1
VDAC_BUFF
VN
VDRP
VOSNS +
VO
FB
EAOUT
Rdrp
Rctmp1
tcmp2
Cvdac
vdac
Rosc
Css/De
setpt
To Regulato
To Rtherm
fb
fb1
fb
Ccp
cp
LGND
PLANE
Voltage
Remote
Sense
To
Phase ICs
Analog
To Thermisto
mon1