IR3502B
Page 34 of 38 V3.2
LAYOUT GUIDELINES
The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB
layout, therefore minimizing the noise coupled to the IC.
Dedicate at least one middle layer for a ground plane LGND.
Connect the ground tab under the control IC to LGND plane through a via.
Place VCCL decoupling capacitor VCCL as close as possible to VCCL and LGND pins.
Place the following critical components on the same layer as control IC and position them as close as possible
to the respective pins, R
OSC, RVDAC, CVDAC, and CSS/DEL. Avoid using any via for the connection.
Place the compensation components on the same layer as control IC and position them as close as possible to
EAOUT, FB, VO and VDRP pins. Avoid using any via for the connection.
Use Kelvin connections for the remote voltage sense signals, VOSNS+ and VOSNS-, and avoid crossing over
the fast transition nodes, i.e. switching nodes, gate drive signals and bootstrap nodes.
Avoid analog control bus signals, VDAC, IIN, and especially EAOUT, crossing over the fast transition nodes.
Separate digital bus, CLKOUT, PHSOUT and PHSIN from the analog control bus and other compensation
components.
HOTSETVCCLDRV
PGOOD
IMON ENABLE
VOSNS –
To
Phase ICs
Digital
To VCCL
GND
SS/DEL
VDAC
IIN
VRHOT
VSETPT VID3
VID4
ROSC
VID5
VID6
VID7
VCCL
R
tcmp3
PHSOUT
CLKOUT
PHSIN
VID2
VID1
VID0
C
mon
R
mon
C
vccl2
To SYSTEM
C
cp1
Rhotset2
Rhotset1
VDAC_BUFF
VN
VDRP
VOSNS +
VO
FB
EAOUT
Rdrp
Rctmp1
R
tcmp2
Cvdac
R
vdac
Rosc
Css/De
l
R
setpt
To Regulato
r
To Rtherm
R
fb
R
fb1
C
fb
Ccp
R
cp
LGND
PLANE
Voltage
Remote
Sense
To
Phase ICs
Analog
To Thermisto
r
R
mon1
IR3502B
Page 35 of 38 V3.2
PCB Metal and Component Placement
Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should
be 0.2mm to prevent shorting.
Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension + 0.05mm
inboard extension. The outboard extension ensures a large and inspectable toe fillet, and the inboard
extension will accommodate any part misalignment and ensure a fillet.
Center pad land length and width should be equal to maximum part pad length and width. However, the
minimum metal to metal spacing should be 0.17mm for 2 oz. Copper ( 0.1mm for 1 oz. Copper and
0.23mm for 3 oz. Copper)
Four 0.30mm diameter vias shall be placed in the center of the pad land and connected to ground to
minimize the noise effect on the IC.
No pcb traces should be routed nor vias placed under any of the 4 corners of the IC package. Doing so
can cause the IC to rise up from the pcb resulting in poor solder joints to the IC leads.
IR3502B
Page 36 of 38 V3.2
Solder Resist
The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder
resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non
Solder Mask Defined (NSMD). Therefore pulling the S/R 0.06mm will always ensure NSMD pads.
The minimum solder resist width is 0.13mm.
At the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a
fillet so a solder resist width of 0.17mm remains.
The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto
the copper of 0.06mm to accommodate solder resist mis-alignment. In 0.5mm pitch cases it is allowable
to have the solder resist opening for the land pad to be smaller than the part pad.
Ensure that the solder resist in-between the lead lands and the pad land is 0.15mm due to the high
aspect ratio of the solder resist strip separating the lead lands from the pad land.
The vias in the land pad should be tented or plugged from bottom boardside with solder resist.

IR3502BMTRPBF

Mfr. #:
Manufacturer:
Infineon Technologies
Description:
Power Management Specialized - PMIC X-PHASE CONTROL IC AMD SVID CTRL IC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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