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BOB-09981

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P62
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SC16IS740_750_760_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 13 May 2008 22 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
[1] These registers are accessible only when LCR[7] = 0.
[2] These bits in can only be modified if register bit EFR[4] is enabled.
[3] These bits are reserved and should be set to 0.
[4] Only available on the SC16IS750/SC16IS760.
[5] After Receive FIFO or Transmit FIFO reset (through FCR[1:0]), the user must wait at least 2 × T
clk
of XTAL1 before reading or writing data to RHR and THR, respectively.
[6] Burst reads on the serial interface (that is, reading multiple elements on the I
2
C-bus without a STOP or repeated START condition, or reading multiple elements on the SPI bus
without de-asserting the CS pin), should not be performed on the IIR register.
[7] These registers are accessible only when MCR[2] = 1 and EFR[4] = 1.
[8] IrDA mode slow/fast for SC16IS760, slow only for SC16IS750.
[9] The special register set is accessible only when LCR[7] = 1 and not 0xBF.
[10] Enhanced Feature Registers are only accessible when LCR = 0xBF.
Special register set
[9]
0x00 DLL bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
0x01 DLH bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
Enhanced register set
[10]
0x02 EFR Auto CTS Auto RTS special
character
detect
enable
enhanced
functions
software flow
control bit 3
software flow
control bit 2
software flow
control bit 1
software flow
control bit 0
R/W
0x04 XON1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
0x05 XON2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
0x06 XOFF1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
0x07 XOFF2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
Table 10. SC16IS740/750/760 internal registers
…continued
Register
address
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W
SC16IS740_750_760_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 13 May 2008 23 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.1 Receive Holding Register (RHR)
The receiver section consists of the Receiver Holding Register (RHR) and the Receiver
Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data
from the RX pin. The data is converted to parallel data and moved to the RHR. The
receiver section is controlled by the Line Control Register. If the FIFO is disabled, location
zero of the FIFO is used to store the characters.
8.2 Transmit Holding Register (THR)
The transmitter section consists of the Transmit Holding Register (THR) and the Transmit
Shift Register (TSR). The THR is actually a 64-byte FIFO. The THR receives data and
shifts it into the TSR, where it is converted to serial data and moved out on the TX pin. If
the FIFO is disabled, the FIFO is still used to store the byte. Characters are lost if overflow
occurs.
8.3 FIFO Control Register (FCR)
This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting
transmitter and receiver trigger levels. Table 11 shows FIFO Control Register bit settings.
Table 11. FIFO Control Register bits description
Bit Symbol Description
7:6 FCR[7](MSB),
FCR[6] (LSB)
RX trigger. Sets the trigger level for the RX FIFO.
00 = 8 characters
01 = 16 characters
10 = 56 characters
11 = 60 characters
5:4 FCR[5](MSB),
FCR[4] (LSB)
TX trigger. Sets the trigger level for the TX FIFO.
00 = 8 spaces
01 = 16 spaces
10 = 32 spaces
11 = 56 spaces
FCR[5:4] can only be modified and enabled when EFR[4] is set. This is
because the transmit trigger level is regarded as an enhanced function.
3 FCR[3] reserved
2 FCR[2]
[1]
reset TX FIFO
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
level logic (the Transmit Shift Register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO.
1 FCR[1]
[1]
reset RX FIFO
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
level logic (the Receive Shift Register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO.
0 FCR[0] FIFO enable
logic 0 = disable the transmit and receive FIFO (normal default condition)
logic 1 = enable the transmit and receive FIFO
SC16IS740_750_760_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 13 May 2008 24 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
[1] FIFO reset requires at least two XTAL1 clocks, therefore, they cannot be reset without the presence of the
XTAL1 clock.
8.4 Line Control Register (LCR)
This register controls the data communication format. The word length, number of stop
bits, and parity type are selected by writing the appropriate bits to the LCR. Table 12
shows the Line Control Register bit settings.
Table 12. Line Control Register bits description
Bit Symbol Description
7 LCR[7] divisor latch enable
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
6 LCR[6] Break control bit. When enabled, the break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0 state).
This condition exists until disabled by setting LCR[6] to a logic 0.
logic 0 = no TX break condition (normal default condition).
logic 1 = forces the transmitter output (TX) to a logic 0 to alert the
communication terminal to a line break condition
5 LCR[5] Set parity. LCR[5] selects the forced parity format (if LCR[3] = 1).
logic 0 = parity is not forced (normal default condition).
LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1
for the transmit and receive data.
LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0
for the transmit and receive data.
4 LCR[4] parity type select
logic 0 = odd parity is generated (if LCR[3] = 1)
logic 1 = even parity is generated (if LCR[3] = 1)
3 LCR[3] parity enable
logic 0 = no parity (normal default condition).
logic 1 = a parity bit is generated during transmission and the receiver
checks for received parity
2 LCR[2] Number of stop bits. Specifies the number of stop bits.
0 to 1 stop bit (word length = 5, 6, 7, 8)
1 to 1.5 stop bits (word length = 5)
1 = 2 stop bits (word length = 6, 7, 8)
1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be
transmitted or received; see
Table 15.
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BOB-09981

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Buy BOB-09981
Manufacturer:
SparkFun
Description:
Interface Development Tools I2C/SPI-to-UART Breakout - SC16IS750
Lifecycle:
New from this manufacturer.
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