SC16IS740_750_760_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 13 May 2008 47 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
14. Dynamic characteristics
[1] A detailed description of the I
2
C-bus specification, with applications, is given in user manual UM10204:
“I
2
C-bus specification and user
manual”
. This may be found at www.nxp.com/acrobat_download/usermanuals/UM10204_3.pdf.
[2] Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if SDA is held LOW for a
minimum of 25 ms.
[3] Only applicable to the SC16IS750 and SC16IS760.
[4] 2 XTAL1 clocks or 3 µs, whichever is less.
Table 37. I
2
C-bus timing specifications
[1]
All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;
V
DD
= 2.5 V
±
0.2 V, T
amb
=
−
40
°
Cto+85
°
C; or V
DD
= 3.3 V
±
0.3 V, T
amb
=
−
40
°
Cto+95
°
C; and refer to V
IL
and V
IH
with
an input voltage of V
SS
to V
DD
. All output load = 25 pF, except SDA output load = 400 pF.
Symbol Parameter Conditions Standard mode
I
2
C-bus
Fast mode
I
2
C-bus
Unit
Min Max Min Max
f
SCL
SCL clock frequency
[2]
0 100 0 400 kHz
t
BUF
bus free time between a STOP and START
condition
4.7 - 1.3 - µs
t
HD;STA
hold time (repeated) START condition 4.0 - 0.6 - µs
t
SU;STA
set-up time for a repeated START
condition
4.7 - 0.6 - µs
t
SU;STO
set-up time for STOP condition 4.7 - 0.6 - µs
t
HD;DAT
data hold time 0 - 0 - ns
t
VD;ACK
data valid acknowledge time - 0.6 - 0.6 µs
t
VD;DAT
data valid time SCL LOW to
data out valid
- 0.6 - 0.6 ns
t
SU;DAT
data set-up time 250 - 150 - ns
t
LOW
LOW period of the SCL clock 4.7 - 1.3 - µs
t
HIGH
HIGH period of the SCL clock 4.0 - 0.6 - µs
t
f
fall time of both SDA and SCL signals - 300 - 300 ns
t
r
rise time of both SDA and SCL signals - 1000 - 300 ns
t
SP
pulse width of spikes that must be
suppressed by the input filter
- 50 - 50 ns
t
d1
I
2
C-bus GPIO output valid time
[3]
0.5 - 0.5 - µs
t
d2
I
2
C-bus modem input interrupt valid time 0.2 - 0.2 - µs
t
d3
I
2
C-bus modem input interrupt clear time 0.2 - 0.2 - µs
t
d4
I2C input pin interrupt valid time 0.2 - 0.2 - µs
t
d5
I2C input pin interrupt clear time 0.2 - 0.2 - µs
t
d6
I
2
C-bus receive interrupt valid time 0.2 - 0.2 - µs
t
d7
I
2
C-bus receive interrupt clear time 0.2 - 0.2 - µs
t
d8
I
2
C-bus transmit interrupt clear time 1.0 - 0.5 - µs
t
d15
SCL delay time after reset
[4]
3-3-µs
t
w(rst)
reset pulse width 3 - 3 - µs
