BOB-09981 Datasheet BOB-09981 | P31-P33

Product data sheet Rev. 06 — 13 May 2008 31 of 62

NXP Semiconductors

SC16IS740/750/760

Single UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.10 Enhanced Features Register (EFR)

This 8-bit register enables or disables the enhanced features of the UART. Table 22 shows

the enhanced feature register bit settings.

8.11 Division registers (DLL, DLH)

These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock

in the baud rate generator. DLH stores the most signiﬁcant part of the divisor. DLL stores

the least signiﬁcant part of the divisor.

Remark: DLL and DLH can only be written to before Sleep mode is enabled, that is,

before IER[4] is set.

Table 22. Enhanced Features Register bits description

Bit Symbol Description

7 EFR[7]

CTS ﬂow control enable

logic 0 =

CTS ﬂow control is disabled (normal default condition)

logic 1 =

CTS ﬂow control is enabled. Transmission will stop when a HIGH

signal is detected on the

CTS pin.

6 EFR[6]

RTS ﬂow control enable.

logic 0 =

RTS ﬂow control is disabled (normal default condition)

logic 1 =

RTS ﬂow control is enabled. The RTS pin goes HIGH when the

receiver FIFO halt trigger level TCR[3:0] is reached, and goes LOW when

the receiver FIFO resume transmission trigger level TCR[7:4] is reached.

5 EFR[5] Special character detect

logic 0 = Special character detect disabled (normal default condition)

logic 1 = Special character detect enabled. Received data is compared

with Xoff2 data. If a match occurs, the received data is transferred to FIFO

and IIR[4] is set to a logical 1 to indicate a special character has been

detected.

4 EFR[4] Enhanced functions enable bit

logic 0 = disables enhanced functions and writing to IER[7:4], FCR[5:4],

MCR[7:5].

logic 1 = enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5]

so that they can be modiﬁed.

3:0 EFR[3:0] Combinations of software ﬂow control can be selected by programming these

bits. See

Table 3 “Software ﬂow control options (EFR[3:0])”.

Product data sheet Rev. 06 — 13 May 2008 32 of 62

NXP Semiconductors

SC16IS740/750/760

Single UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.12 Transmission Control Register (TCR)

This 8-bit register is used to store the RX FIFO threshold levels to stop/start transmission

during hardware/software ﬂow control. Table 23 shows Transmission Control Register bit

settings.

TCR trigger levels are available from 0 to 60 characters with a granularity of four.

Remark: TCR can only be written to when EFR[4] = 1 and MCR[2] = 1. The programmer

must program the TCR such that TCR[3:0] > TCR[7:4]. There is no built-in hardware

check to make sure this condition is met. Also, the TCR must be programmed with this

condition before auto RTS or software ﬂow control is enabled to avoid spurious operation

of the device.

8.13 Trigger Level Register (TLR)

This 8-bit register is used to store the transmit and received FIFO trigger levels used for

interrupt generation. Trigger levels from 4 to 60 can be programmed with a granularity

of 4. Table 24 shows trigger level register bit settings.

Remark: TLR can only be written to when EFR[4] = 1 and MCR[2] = 1. If TLR[3:0] or

TLR[7:4] are logical 0, the selectable trigger levels via the FIFO Control Register (FCR)

are used for the transmit and receive FIFO trigger levels. Trigger levels from 4 characters

to 60 characters are available with a granularity of four. The TLR should be programmed

for

⁄

, where N is the desired trigger level.

When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the trigger

level setting deﬁned in FCR. If TLR has non-zero trigger level value, the trigger level

deﬁned in FCR is discarded. This applies to both transmit FIFO and receive FIFO trigger

level setting.

When TLR is used for RX trigger level control, FCR[7:6] should be left at the default state,

that is, ‘00’.

8.14 Transmitter FIFO Level register (TXLVL)

This register is a read-only register, it reports the number of spaces available in the

transmit FIFO.

Table 23. Transmission Control Register bits description

Bit Symbol Description

7:4 TCR[7:4] RX FIFO trigger level to resume

3:0 TCR[3:0] RX FIFO trigger level to halt transmission

Table 24. Trigger Level Register bits description

Bit Symbol Description

7:4 TLR[7:4] RX FIFO trigger levels (4 to 60), number of characters available.

3:0 TLR[3:0] TX FIFO trigger levels (4 to 60), number of spaces available.

Table 25. Transmitter FIFO Level register bits description

Bit Symbol Description

7 - not used; set to zeros

6:0 TXLVL[6:0] number of spaces available in TX FIFO, from 0 (0x00) to 64 (0x40)

Product data sheet Rev. 06 — 13 May 2008 33 of 62

NXP Semiconductors

SC16IS740/750/760

Single UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.15 Receiver FIFO Level register (RXLVL)

This register is a read-only register, it reports the ﬁll level of the receive FIFO. That is, the

number of characters in the RX FIFO.

8.16 Programmable I/O pins Direction register (IODir)

This register is only available on the SC16IS750 and SC16IS760. This register is used to

program the I/O pins direction. Bit 0 to bit 7 controls GPIO0 to GPIO7.

Remark: If there is a pending input (GPIO) interrupt and IODir is written, this pending

interrupt will be cleared, that is, the interrupt signal will be negated.

8.17 Programmable I/O pins State Register (IOState)

This register is only available on the SC16IS750 and SC16IS760. When ‘read’, this

transferred to the corresponding IO pin programmed as output.

8.18 I/O Interrupt Enable Register (IOIntEna)

This register is only available on the SC16IS750 and SC16IS760. This register enables

the interrupt due to a change in the I/O conﬁgured as inputs. If GPIO[7:4] are programmed

as modem pins, their interrupt generation must be enabled via IER register bit 3. In this

case bit 7 to bit 4 of IOIntEna will have no effect on GPIO[7:4].

Table 26. Receiver FIFO Level register bits description

Bit Symbol Description

7 - not used; set to zeros

6:0 RXLVL[6:0] number of characters stored in RX FIFO, from 0 (0x00) to 64 (0x40)

Table 27. IODir register bits description

Bit Symbol Description

7:0 IODir set GPIO pins [7:0] to input or output

0 = input

1 = output

Table 28. IOState register bits description

Bit Symbol Description

7:0 IOState Write this register:

set the logic level on the output pins

0 = set output pin to zero

1 = set output pin to one

Read this register:

return states of all pins

Table 29. IOIntEna register bits description

Bit Symbol Description

7:0 IOIntEna input interrupt enable

0 = a change in the input pin will not generate an interrupt

1 = a change in the input will generate an interrupt

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BOB-09981

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Manufacturer:

SparkFun

Description:

Interface Development Tools I2C/SPI-to-UART Breakout - SC16IS750

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