SC16IS740_750_760_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 13 May 2008 50 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
[1] Applies to external clock, crystal oscillator max. 24 MHz.
[2]
Table 38. f
XTAL
dynamic characteristics
V
DD
= 2.5 V
±
0.2 V, T
amb
=
−
40
°
Cto+85
°
C; or V
DD
= 3.3 V
±
0.3 V, T
amb
=
−
40
°
Cto+95
°
C
Symbol Parameter Conditions V
DD
= 2.5 V V
DD
= 3.3 V Unit
Min Max Min Max
t
w1
clock pulse duration 10 - 6 - ns
t
w2
clock pulse duration 10 - 6 - ns
f
XTAL
frequency on pin XTAL
[1][2]
- 48 - 80 MHz
XTAL
1
t
w3
-------
=
Fig 33. External clock timing
EXTERNAL
CLOCK
002aaa112
t
w3
t
w2
t
w1
Table 39. SC16IS740/750 SPI-bus timing specifications
All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;
V
DD
= 2.5 V
±
0.2 V, T
amb
=
−
40
°
Cto+85
°
C; or V
DD
= 3.3 V
±
0.3 V, T
amb
=
−
40
°
Cto+95
°
C; and refer to V
IL
and V
IH
with
an input voltage of V
SS
to V
DD
. All output load = 25 pF, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
t
TR
CS HIGH to SO 3-state delay time C
L
= 100 pF - - 100 ns
t
CSS
CS to SCLK setup time 100 - - ns
t
CSH
CS to SCLK hold time 20 - - ns
t
DO
SCLK fall to SO valid delay time C
L
= 100 pF - - 100 ns
t
DS
SI to SCLK setup time 100 - - ns
t
DH
SI to SCLK hold time 20 - - ns
t
CP
SCLK period t
CL
+ t
CH
250 - - ns
t
CH
SCLK HIGH time 100 - - ns
t
CL
SCLK LOW time 100 - - ns
t
CSW
CS HIGH pulse width 200 - - ns
t
d9
SPI output data valid time 200 - - ns
t
d10
SPI modem output data valid time 200 - - ns
t
d11
SPI transmit interrupt clear time 200 - - ns
t
d12
SPI modem input interrupt clear time 200 - - ns
t
d13
SPI interrupt clear time 200 - - ns
t
d14
SPI receive interrupt clear time 200 - - ns
t
w(rst)
reset pulse width 3 - - µs
