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BOB-09981

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P62
SC16IS740_750_760_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 13 May 2008 7 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
6.2 Pin description
a. I
2
C-bus interface b. SPI interface
Fig 7. Pin configuration for HVQFN24
RTS
GPIO7/RI
GPIO6/CD
RX
TX
CTS
A0
I2C
V
DD
XTAL1
RESET
XTAL2
n.c.
A1
IRQ
SDA
SCL
GPIO0
002aab015
GPIO5/DTR
GPIO4/DSR
GPIO3
GPIO2
GPIO1
V
SS
SC16IS750IBS
SC16IS760IBS
Transparent top view
terminal 1
index area
6
13
5
14
4 15
3 16
2 17
1
18
7
8
9
10
11
12
24
23
22
21
20
19
RTS
GPIO7/RI
GPIO6/CD
RX
TX
CTS
CS
SPI
V
DD
XTAL1
RESET
XTAL2
SO
SI
IRQ
V
SS
SCLK
GPIO0
002aab401
GPIO5/DTR
GPIO4/DSR
GPIO3
GPIO2
GPIO1
V
SS
SC16IS750IBS
SC16IS760IBS
Transparent top view
terminal 1
index area
6
13
5
14
4 15
3 16
2 17
1
18
7
8
9
10
11
12
24
23
22
21
20
19
Table 2. Pin description
Symbol Pin Type Description
TSSOP16 TSSOP24 HVQFN24
CTS 11 1 22 I UART clear to send (active LOW). A logic 0 (LOW) on the CTS
pin indicates the modem or data set is ready to accept transmit
data from the SC16IS740/750/760. Status can be tested by
reading MSR[4]. This pin only affects the transmit and receive
operations when auto
CTS function is enabled via the Enhanced
Feature Register EFR[7] for hardware flow control operation.
TX 12 2 23 O UART transmitter output. During the local Loopback mode, the
TX output pin is disabled and TX data is internally connected to
the UART RX input.
RX 13 3 24 I UART receiver input. During the local Loopback mode, the RX
input pin is disabled and TX data is connected to the UART RX
input internally.
RESET 14 4 1 I device hardware reset (active LOW)
[1]
XTAL1 15 5 2 I Crystal input or external clock input. Functions as a crystal input
or as an external clock input. A crystal can be connected
between XTAL1 and XTAL2 to form an internal oscillator circuit
(see
Figure 15). Alternatively, an external clock can be
connected to this pin.
XTAL2 16 6 3 O Crystal output or clock output. (See also XTAL1.) XTAL2 is used
as a crystal oscillator output.
V
DD
1 7 4 - power supply
I2C/
SPI 8 8 5 I I
2
C-bus or SPI interface select. I
2
C-bus interface is selected if
this pin is at logic HIGH. SPI interface is selected if this pin is at
logic LOW.
SC16IS740_750_760_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 13 May 2008 8 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
[1] See Section 7.4 “Hardware reset, Power-On Reset (POR) and software reset”
[2] Selectable with IOControl register bit 1.
CS/A0 2 9 6 I SPI chip select or I
2
C-bus device address select A0. If SPI
configuration is selected by I2C/
SPI pin, this pin is the SPI chip
select pin (Schmitt-trigger, active LOW). If I
2
C-bus configuration
is selected by I2C/
SPI pin, this pin along with A1 pin allows user
to change the device’s base address.
SI/A1 3 10 7 I SPI data input pin or I
2
C-bus device address select A1. If SPI
configuration is selected by I2C/
SPI pin, this is the SPI data
input pin. If I
2
C-bus configuration is selected by I2C/SPI pin, this
pin along with A0 pin allows user to change the device’s base
address. To select the device address, please refer to
Table 32.
SO 4 11 8 O SPI data output pin. If SPI configuration is selected by I2C/
SPI
pin, this is a 3-stateable output pin. If I
2
C-bus configuration is
selected by I2C/
SPI pin, this pin function is undefined and must
be left as n.c. (not connected).
SCL/SCLK 5 12 9 I I
2
C-bus or SPI input clock.
SDA 6 13 10 I/O I
2
C-bus data input/output, open-drain if I
2
C-bus configuration is
selected by I2C/
SPI pin. If SPI configuration is selected then this
pin is an undefined pin and must be connected to V
SS
.
IRQ 7 14 11 O Interrupt (open-drain, active LOW). Interrupt is enabled when
interrupt sources are enabled in the Interrupt Enable Register
(IER). Interrupt conditions include: change of state of the input
pins, receiver errors, available receiver buffer data, available
transmit buffer space, or when a modem status flag is detected.
An external resistor (1 kΩ for 3.3 V, 1.5 kΩ for 2.5 V) must be
connected between this pin and V
DD
.
GPIO0 - 15 12 I/O programmable I/O pin
GPIO1 - 16 13 I/O programmable I/O pin
GPIO2 - 17 14 I/O programmable I/O pin
GPIO3 - 18 15 I/O programmable I/O pin
GPIO4/
DSR - 20 17 I/O programmable I/O pin or modem’s DSR pin
[2]
GPIO5/DTR - 21 18 I/O programmable I/O pin or modem’s DTR pin
[2]
GPIO6/CD - 22 19 I/O programmable I/O pin or modem’s CD pin
[2]
GPIO7/RI - 23 20 I/O programmable I/O pin or modem’s RI pin
[2]
RTS 10 24 21 O UART request to send (active LOW). A logic 0 on the RTS pin
indicates the transmitter has data ready and waiting to send.
Writing a logic 1 in the modem control register MCR[1] will set
this pin to a logic 0, indicating data is available. After a reset this
pin is set to a logic 1. This pin only affects the transmit and
receive operations when auto
RTS function is enabled via the
Enhanced Feature Register (EFR[6]) for hardware flow control
operation.
V
SS
91916
[3]
- ground
V
SS
- - center
pad
[3]
- The center pad on the back side of the HVQFN24 package is
metallic and should be connected to ground on the
printed-circuit board.
Table 2. Pin description
…continued
Symbol Pin Type Description
TSSOP16 TSSOP24 HVQFN24
SC16IS740_750_760_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 13 May 2008 9 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
[3] HVQFN24 package die supply ground is connected to both V
SS
pins and exposed center pad. V
SS
pins must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
7. Functional description
The UART will perform serial-to-I
2
C conversion on data characters received from
peripheral devices or modems, and I
2
C-to-serial conversion on data characters
transmitted by the host. The complete status the SC16IS740/750/760 UART can be read
at any time during functional operation by the host.
The SC16IS740/750/760 can be placed in an alternate mode (FIFO mode) relieving the
host of excessive software overhead by buffering received/transmitted characters. Both
the receiver and transmitter FIFOs can store up to 64 characters (including three
additional bits of error status per character for the receiver FIFO) and have selectable or
programmable trigger levels.
The SC16IS740/750/760 has selectable hardware flow control and software flow control.
Hardware flow control significantly reduces software overhead and increases system
efficiency by automatically controlling serial data flow using the RTS output and CTS input
signals. Software flow control automatically controls data flow by using programmable
Xon/Xoff characters.
The UART includes a programmable baud rate generator that can divide the timing
reference clock input by a divisor between 1 and (2
16
– 1).
7.1 Trigger levels
The SC16IS740/750/760 provides independently selectable and programmable trigger
levels for both receiver and transmitter interrupt generation. After reset, both transmitter
and receiver FIFOs are disabled and so, in effect, the trigger level is the default value of
one character. The selectable trigger levels are available via the FCR. The programmable
trigger levels are available via the TLR. If TLR bits are cleared then selectable trigger level
in FCR is used. If TLR bits are not cleared then programmable trigger level in TLR is used.
7.2 Hardware flow control
Hardware flow control is comprised of auto CTS and auto RTS (see Figure 8). Auto CTS
and auto RTS can be enabled/disabled independently by programming EFR[7:6].
With auto CTS, CTS must be active before the UART can transmit data.
Auto RTS only activates the RTS output when there is enough room in the FIFO to receive
data and de-activates the RTS output when the RX FIFO is sufficiently full. The halt and
resume trigger levels in the TCR determine the levels at which RTS is
activated/deactivated. If TCR bits are cleared then selectable trigger levels in FCR are
used in place of TCR.
If both auto CTS and auto RTS are enabled, when RTS is connected to CTS, data
transmission does not occur unless the receiver FIFO has empty space. Thus, overrun
errors are eliminated during hardware flow control. If not enabled, overrun errors occur if
the transmit data rate exceeds the receive FIFO servicing latency.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P62

BOB-09981

Mfr. #:
Buy BOB-09981
Manufacturer:
SparkFun
Description:
Interface Development Tools I2C/SPI-to-UART Breakout - SC16IS750
Lifecycle:
New from this manufacturer.
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