SC16IS740_750_760_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 13 May 2008 42 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
Table 33 and Table 34 show the bits’ presentation at the subaddress byte for I
2
C-bus and
SPI interfaces. Bit 0 is not used, bits 2:1 select the channel, bits 6:3 select one of the
UART internal registers. Bit 7 is not used with the I
2
C-bus interface, but it is used by the
SPI interface to indicate a read or a write operation.
The register read cycle (see Figure 23) commences in a similar manner, with the master
sending a slave address with the direction bit set to ‘write’ with a following subaddress.
Then, in order to reverse the direction of the transfer, the master issues a repeated START
followed again by the device address, but this time with the direction bit set to ‘read’. The
data bytes starting at the internal subaddress will be clocked out of the device, each
followed by a master-generated acknowledge. The last byte of the read cycle will be
followed by a negative acknowledge, signalling the end of transfer. The cycle is terminated
by a STOP signal.
White block: host to SC16IS740/750/760
Grey block: SC16IS740/750/760 to host
(1) See Table 33 for additional information.
Fig 22. Master writes to slave
S SLAVE ADDRESS
002aab047
W A REGISTER ADDRESS
(1)
A nDATA A P
White block: host to SC16IS740/750/760
Grey block: SC16IS740/750/760 to host
(1) See Table 33 for additional information.
Fig 23. Master read from slave
S SLAVE ADDRESS
002aab048
W A REGISTER ADDRESS
(1)
A
NA P
S SLAVE ADDRESS R A
nDATA A LAST DATA
Table 33. Register address byte (I
2
C)
Bit Name Function
7 - not used
6:3 A[3:0] UART’s internal register select
2:1 CH1, CH0 channel select: CH1 = 0, CH0 = 0
Other values are reserved and should not be used.
0 - not used
