NCV7513B
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DETAILED OPERATING DESCRIPTION
General
The NCV7513B is a six channel general purpose
low−side pre−driver for controlling and protecting N−type
logic level MOSFETs. While specifically designed for
driving MOSFETs with resistive, inductive or lamp loads
in automotive applications, the device is also suitable for
industrial and commercial applications. Programmable
fault detection and protection modes allow the NCV7513B
to accommodate a wide range of external MOSFETs and
loads, providing the user with flexible application
solutions. Separate power supply pins are provided
for low and high current paths to improve analog
accuracy and digital signal integrity. ON Semiconductor’s
SMARTDISCRETES
TM
clamp MOSFETs, such as the
NID9N05CL, are recommended when driving unclamped
inductive loads.
Power Up/Down Control
The NCV7513B’s powerup/down control prevents
spurious output operation by monitoring the V
CC1
power
supply. An internal Power−On Reset (POR) circuit causes
all GAT
X
outputs to be held low until sufficient voltage is
available to allow proper control of the device. All internal
registers are initialized to their default states, fault data is
cleared, and the open−drain fault (FLTB) and status
(STAB) flags are disabled.
When V
CC1
exceeds the POR threshold, outputs and
flags are enabled and the device is ready to accept input
data. When V
CC1
falls below the POR threshold during
power down, flags are reset and disabled and all GAT
X
outputs are driven and held low until V
CC1
falls below
about 0.7 V.
SPI Communication
The NCV7513B is a 16−bit SPI slave device. SPI
communication between the host and the NCV7513B may
either be parallel via individual CSB addressing or
daisy−chained through other devices using a compatible
SPI protocol.
The active−low CSB chip select input has a pullup
current source. The SI and SCLK inputs have pulldown
current sources. The recommended idle state for SCLK is
low. The tri−state SO line driver can be supplied with either
3.3 or 5.0 V and is powered via the device’s V
DD
and V
SS
pins.
The NCV7513B employs frame error detection that
requires integer multiples of 16 SCLK cycles during each
CSB high−low−high cycle (valid communication frame.)
A frame error does not affect the flags. The CSB input
controls SPI data transfer and initializes the selected
device’s frame error and fault reporting logic.
The host initiates communication when a selected
device’s CSB pin goes low. Output (fault) data is
simultaneously sent MSB first from the SO pin while input
(command) data is received MSB first at the SI pin under
synchronous control of the master’s SCLK signal while
CSB is held low (Figure 10). Fault data changes on the
falling edge of SCLK and is guaranteed valid before the
next rising edge of SCLK. Command data received must be
valid before the rising edge of SCLK.
When CSB goes low, frame error detection is initialized,
latched fault data is transferred to the SPI, and the FLTB
flag is disabled and reset if previously set. Data for faults
detected while CSB is low are ignored but will be captured
if still present after CSB goes high.
If a valid frame has been received when CSB goes high,
the last multiple of 16 bits received is decoded into
command data, and FLTB is re−enabled. Latched
(previous) fault data is cleared and current fault data is
captured. The FLTB flag will be set if a fault is detected.
If a frame error is detected when CSB goes high, new
command data is ignored, and previous fault data remains
latched and available for retrieval during the next valid
frame. The FLTB flag will be set if a fault (not a frame
error) is detected.
Z
Z
X X
CSB
SCLK
SI
SO
1 2 3 14 15 16
MSB LSB
B15 B14 B13 B12 − B3 B2 B1 B0
UKN
B15 B14 B13 B2 B1 B0
Note: X=Don’t Care, Z=Tri−State, UKN=Unknown Data
4 − 13
B12 − B3
Figure 10. SPI Communication Frame Format
