OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

NCV7513BFTR2G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
NCV7513B
www.onsemi.com
13
Table 4. Refresh and Reference Register
A
2
A
1
A
0
D
5
D
4
D
3
D
2
D
1
D
0
0 1 0 R
5
R
4
R
3
R
2
R
1
R
0
CHANNELS 5−3 CHANNELS 2−0
25% V
FLTREF
X 0 0 X 0 0
50% V
FLTREF
X 0 1 X 0 1
75% V
FLTREF
X 1 0 X 1 0
V
FLTREF
X 1 1 X 1 1
t
FR
= 10 ms X X X 0 X X
t
FR
= 40 ms X X X 1 X X
t
FR
= 10 ms 0 X X X X X
t
FR
= 40 ms 1 X X X X X
Flag Mask – Register 3
The drain feedback from each channel’s DRN
X
input is
combined with the channel’s K
X
mask bit (Table 5). When
K
X
= 1, a channel’s mask is cleared and its feedback to the
FLTB and STAB flags is enabled. At powerup, each bit is
set to 0 (all masks set).
Table 5. Flag Mask Register
A
2
A
1
A
0
D
5
D
4
D
3
D
2
D
1
D
0
0 1 1 K
5
K
4
K
3
K
2
K
1
K
0
0 = MASK SET
1 = MASK CLEAR
The STAB flag is influenced when a mask bit changes
CLR→SET after one valid SPI frame. FLTB is influenced
after two valid SPI frames. This is correct behavior for
FLTB since, while a fault persists, the FLTB will be set
when CSB goes LO→HI at the end of an SPI frame. The
mask instruction is decoded after CSB goes LO→HI so
FLTB will only reflect the mask bit change after the next
SPI frame. Both FLTB and STAB require only one valid
SPI frame when a mask bit changes SET→CLR.
Null Register – Register 4
Fault information is always returned when any register
is addressed. The null register (Table 6) provides a way to
read back fault information without regard to the content
of D
X
.
Table 6. Null Register
A
2
A
1
A
0
D
5
D
4
D
3
D
2
D
1
D
0
1 X X X X X X X X
Gate Driver Control and Enable
Each GAT
X
output may be turned on by either its
respective parallel IN
X
input or the internal G
X
(Gate
Select) register bit via SPI communication. The device’s
common ENA
X
enable inputs can be used to implement
global control functions, such as system reset, overvoltage
or input override by a watchdog controller. Each parallel
input and the ENA2 input have individual internal
pulldown current sources. The ENA1 input has an internal
pulldown resistor. Unused parallel inputs should be
connected to GND and unused enable inputs should be
connected to V
CC1
. Parallel input is recommended when
low frequency (v2.0 kHz) PWM operation of the outputs
is desired.
ENA2 disables all GAT
X
outputs when brought low.
When ENA1 is brought low, all GAT
X
outputs, the timer
clock, and the flags are disabled. The fault and gate
registers are cleared and the flags are reset. New serial G
X
data is ignored while ENA1 is low but other registers can
be programmed.
When both the ENA1 and ENA2 inputs are high, the
outputs will reflect the current parallel or serial input states.
This allows ENA1 to be used to perform a soft reset and
ENA2 to be used to disable the GAT
X
outputs during
initialization of the NCV7513B.
The IN
X
input state and the G
X
register bit data are
logically combined with the internal (active low)
power−on reset signal (POR), the ENA
X
input states, and
the shorted load state (SHRT
X
) to control the
corresponding GAT
X
output such that:
GAT
X
+ POR · ENA1 · ENA2 · SHRT
x
·(IN
x
) G
x
)
(eq. 1)
NCV7513B
www.onsemi.com
14
The GAT
X
state truth table is given in Table 7.
Table 7. Gate Driver Truth Table
POR ENA1 ENA2 SHRT
X
IN
X
G
X
GAT
X
0 X X X X X L
1 0 0 X X X L
1 0 1 X X X L
1 1 0 X X X L
1 1 1 1 0 0 L
1 1 1 1 1 X H
1 1 1 1 X 1 H
1 1 1 0 X X L
1 1→0 1 X X →0 →L
1 1 1→0 X X G
X
→L
1 1 0→1 X 0 G
X
→G
X
Gate Drivers
The non−inverting GAT
X
drivers are symmetrical
resistive switches (1.80 kW typ.) to the V
CC2
and V
SS
voltages. While the outputs are designed to provide
symmetrical gate drive to an external MOSFET, load
current switching symmetry is dependent on the
characteristics of the external MOSFET and its load.
Figure 12 shows the gate driver block diagram.
DRIVER
VCC2
V
SS
V
SS
G
X
IN
X
ENA1
ENA2
FILTER
TIMER
LATCH OFF /
AUTO RE−TRY
M
X
D
X1
DRN
X
GAT
X
S
_
R
R
2
| R
5
POR
FAULT
DETECTION
D
X0
t
FR
BLANKING
TIMER
ENCODING
LOGIC
EN
SHRT
X
50
1800
Figure 12. Gate Driver Channel
Fault Diagnostics and Behavior
Each channel has independent fault diagnostics and
employs blanking and filter timers to suppress false faults.
An external MOSFET is monitored for fault conditions by
connecting its drain to a channel’s DRN
X
feedback input
through an external series resistor.
When either ENA1 or ENA2 is low, diagnostics are
disabled. When both ENA1 and ENA2 are high,
diagnostics are enabled.
Shorted load (or short to V
LOAD
) faults can be detected
when a driver is on. Open load or short to GND faults can
be detected when a driver is off.
On−state faults will initiate MOSFET protection
behavior, set the FLTB flag and the respective channel’s D
X
bits in the device’s fault latches. Off−state faults will
simply set the FLTB flag and the channel’s D
X
bits.
Fault types are uniquely encoded in a 2−bit per channel
format. Fault information for all channels simultaneously
is retrieved by SPI read (Figure 11). Table 8 shows the
fault−encoding scheme for channel 0. The remaining
channels are identically encoded.
Table 8. Fault Data Encoding
CHANNEL 0 STATUS
D
1
D
0
0 0 NO FAULT
0 1 OPEN LOAD
1 0 SHORT TO GND
1 1 SHORTED LOAD
Blanking and Filter Timers
Blanking timers are used to allow drain feedback to
stabilize after a channel is commanded to change states.
Filter timers are used to suppress glitches while a channel
is in a stable state.
A turn−on blanking timer is started when a channel is
commanded on. Drain feedback is sampled after t
BL(ON)
.
A turn−off blanking timer is started when a channel is
commanded off. Drain feedback is sampled after t
BL(OFF)
.
A filter timer is started when a channel is in a stable state
and a fault detection threshold associated with that state has
been crossed. Drain feedback is sampled after t
FF
.
Blanking timers for all channels are started when both
ENA1 and ENA2 go high or when either ENA
X
goes high
while the other is high. The blanking time for each channel
depends on the commanded state when ENA
X
goes high.
While each channel has independent blanking and filter
timers, the parameters for the t
BL(ON)
, t
BL(OFF)
, and t
FF
times are the same for all channels.
Shorted Load Detection
An external reference voltage applied to the FLTREF
input serves as a common reference for all channels
(Figure 13). The FLTREF voltage must be within the range
of 0 to V
CC1
−2.0 V and can be derived via a voltage divider
between V
CC1
and GND.
Shorted load detection thresholds can be programmed
via SPI in four 25% increments that are ratiometric to the
applied FLTREF voltage. Separate thresholds can be
selected for channels 0−2 and for channels 3−5 (Table 4).
NCV7513B
www.onsemi.com
15
A shorted load fault is detected when a channel’s DRN
X
feedback is greater than its selected fault reference after
either the turn−on blanking or the filter has timed out.
−
+
OA
R
R
R
R
75%
50%
25%
0
2 X 4
DECODER
123
0
2 X 4
DECODER
123
CHANNELS 3−5
CHANNELS 0−2
R1 R0
R4 R3
REGISTER 2
BITS
FLTREF
0 − 3V
RX
1
RX
2
VCC1
VCC1
KELVIN
Figure 13. Shorted Load Reference Generator
Shorted Load Fault Recovery
Shorted load fault disable mode for each channel is
individually SPI programmable via the M
X
bits in the
device’s Disable Mode register (Table 3).
When latch−off mode is selected the corresponding
GAT
X
output is turned off upon detection of a fault. Fault
recovery is initiated by toggling (ON→OFF→ON) the
channel’s respective IN
X
parallel input, serial G
X
bit, or
ENA2.
When auto−retry mode is selected (default mode) the
corresponding GAT
X
output is turned off for the duration
of the programmed fault refresh time (t
FR
) upon detection
of a fault. The output is automatically turned back on (if
still commanded on) when the refresh time ends. The
channel’s DRN
X
feedback is resampled after the turn−on
blanking time. The output will automatically be turned off
if a fault is again detected. This behavior will continue for
as long as the channel is commanded on and the fault
persists.
In either mode, a fault may exist at turn−on or may occur
some time afterward. To be detected, the fault must exist
longer than either t
BL(ON)
at turn−on or longer than t
FF
some time after turn−on. The length of time that a
MOSFET stays on during a shorted load fault is thus limited
to either t
BL(ON)
or t
FF
.
In auto−retry mode, a persistent shorted load fault will
result in a low duty cycle (t
FD
[
t
BL(ON)
/t
FR
) for the
affected channel and help prevent thermal failure of the
channel’s MOSFET.
CAUTION − CONTINUOUS INPUT TOGGLING VIA
IN
X
, G
X
or ENA2 WILL OVERRIDE EITHER DISABLE
MODE. Care should be taken to service a shorted load fault
quickly when one has been detected.
Fault Recovery Refresh Time
Refresh time for shorted load faults is SPI programmable
to one of two values for channels 0−2 (register bit R2) and
for channels 3−5 (register bit R5) via the Refresh and
Reference register (Table 4).
A global refresh timer with taps at nominally 10 ms and
40 ms is used for auto−retry timing. The first faulted
channel triggers the timer and the full refresh period is
guaranteed for that channel. An additional faulted channel
may initially retry immediately after its turn−on blanking
time, but subsequent retries will have the full refresh time
period.
If all channels in a group (e.g. channels 0−2) become
faulted, they will become synchronized to the selected
refresh period for that group. If all channels become faulted
and are set for the same refresh time, all will become
synchronized to the refresh period.
Open Load and Short to GND Detection
A window comparator with fixed references
proportional to V
CC1
along with a pair of bias currents is
used to detect open load or short to GND faults when a
channel is off. Each channel’s DRN
X
feedback is compared
to the references after either the turn−off blanking or the
filter has timed out. Figure 14 shows the DRN
X
bias and
fault detection zones. The diagnostics are disabled and the
bias currents are turned off when ENA
X
is low.
No fault is detected if the feedback voltage at DRN
X
is
greater than the V
OL
open load reference. If the feedback
is less than the V
SG
short to GND reference, a short to GND
fault is detected. If the feedback is less than V
OL
and
greater than V
SG
, an open load fault is detected.
V
CTR
V
SG
V
OL
−I
SG
I
OL
0
V
DRNX
I
DRNX
Open
Load
Short to
GND
No
Fault
Figure 14. DRN
X
Bias and Fault Detection Zones
Figure 15 shows the simplified detection circuitry. Bias
currents I
SG
and I
OL
are applied to a bridge along with bias
voltage V
CTR
(50% V
CC1
typ.).
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

NCV7513BFTR2G

Mfr. #:
Buy NCV7513BFTR2G
Manufacturer:
ON Semiconductor
Description:
Gate Drivers HEX LO-SIDE PRE-Drvr
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet