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NCV7513BFTR2G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
NCV7513B
www.onsemi.com
19
Shorted Load Recovery
Figure 19 is a continuation of Figure 18. IN
X
is high
when the auto−retry timer ends. GAT
X
goes high and the
blanking and filter timers are started. The fault is removed
before the blanking timer ends, and DRN
X
starts to fall. As
DRN
X
passes through the V
OL
threshold at “A”, the STAB
flag is set. DRN
X
continues to fall and settles below the
FLTREF threshold.
An SPI frame is sent during the blanking time and returns
data indicating a “shorted load” fault. Although the fault is
removed, updates to the fault latches are suppressed while
a blanking or filter timer is active. The same fault is
captured again and FLTB is set when CSB goes high. At
“B” the blanking time ends and the channel’s fault bits will
indicate “no fault” but because the latched data has not yet
been read, the data remains unchanged.
The SPI frame sent after the blanking time ends returns
a “shorted load” fault because the previous frame occurred
during the blanking time. Since the channel’s fault bits
indicate “no fault”, FLTB is reset and the fault latch is
updated at “C” when CSB goes high. If another SPI frame
is sent before “D”, the returned data will indicate “no
fault”.
The channel is commanded off at “D”. GAT
X
goes low
and the timers are started. DRN
X
starts to rise and the STAB
flag is reset as DRN
X
passes through the V
OL
threshold.
The SPI frame sent at “E” returns data indicating “no
fault”.
C
FAULT REMOVED
A
SO
GATx
FLTB
INx
0
1
0
1
0
1
0
1
0
1
CSB
0
1
11 00
0
1
0
1
11 11 11
DRNx
FLTREF
0
VLOAD
VOL
FAULT
LATCH
BLANK
TIMER
FILTER
TIMER
11 11
t
FF
t
BL(ON)
t
FR
INTERNAL
SIGNALS
STAB
0
1
t
BL(OFF)
t
FF
00
D
E
B
Figure 19. Shorted Load Recovery
NCV7513B
www.onsemi.com
20
Short to GND/Open Load
Figure 20 illustrates turn−off with an open or high
resistance load when some capacitance is present at DRN
X
.
In the case of an open load, DRN
X
rises and settles to V
CTR
.
In the case of a high resistance load, DRN
X
may continue
to rise and may eventually settle to V
LOAD
.
The channel is commanded off. GAT
X
goes low and the
timers are started. DRN
X
starts to rise and is below the V
SG
threshold when the blanking time ends at “A”. A short to
GND fault is detected and captured by the fault latch, and
the FLTB flag is set.
DRN
X
continues to rise and as it passes through the V
SG
threshold at “B”, the filter timer is triggered. At the end of
the filter time, the channel’s fault bits will indicate an
“open load” but because the latched data has not yet been
read, the data remains unchanged.
An SPI frame sent shortly after “B” returns data
indicating “short to GND” and the fault latch is updated at
“C” when CSB goes high. The next three frames sent after
“C” return data indicating an “open load”.
The STAB flag is reset at “D” as DRN
X
passes through
the V
OL
threshold. Note that the filter timer is not triggered
as DRN
X
passes from a fault state to a good state. The
channel’s fault bits will indicate “no fault” but because the
latched data has not yet been read, the data remains
unchanged.
The fault latch is updated at “E” when CSB goes high and
the FLTB flag remains reset. The next SPI frame sent
returns data indicating “no fault”.
SO
FLTB
0
1
0
1
0
1
CSB
0
1
00
0
1
0
1
10 01 00
00 10 01 01 01 00
INTERNAL
SIGNALS
FAULT
LATCH
BLANK
TIMER
FILTER
TIMER
01 01
t
FF
t
FF
t
BL(OFF)
GATx
0
1
DRNx
VSG
0
VLOAD
VCTR
VOL
A B C
D
INx
0
1
STAB
0
1
E
Figure 20. Short to GND/Open Load
NCV7513B
www.onsemi.com
21
Table 9. I/O Truth Table
Inputs Outputs*
POR ENA1 ENA2 CSB K
X
IN
X
G
X
DRN
X
GAT
X
FLTB STAB D
X1
D
X0
COMMENT
0 X X X →0 X →0 X →L →Z →Z →00 POR RESET
1 0 X X X X X X L Z Z 00 ENA1
1 1 0 X K
X
X G
X
X L FLTB STAB D
X1
D
X0
ENA2
1 1→0 1 X K
X
X →0 X →L →Z →Z →00 ENA1 RESET
1 1 1→0 X K
X
X G
X
X →L FLTB STAB D
X1
D
X0
ENA2 DISABLE
1 1 X X 0 X X X L Z Z − FLAGS MASKED
1 1 0 X 1 X X > V
OL
L − Z − STAB RESET
1 1 0 X 1 X X < V
OL
L − L − STAB SET
1 1 0 X 1→0 X X < V
OL
L − L→Z − STAB RESET
1 1 0 X 0→1 X X < V
OL
L − Z→L − STAB SET
1 1 1 X 1 0 0 > V
OL
L Z Z 00 FLAGS RESET
1 1 1 1 1 0 0 V
SG
<V<V
OL
L L L 01 FLAGS SET
1 1 1 X 1→0 0 0 V
SG
<V<V
OL
L L L→Z 01 STAB RESET
1 1 1 X 0→1 0 0 V
SG
<V<V
OL
L L 01 STAB SET
1 1 1 1→0 1 0 0 V
SG
<V<V
OL
L L→Z L 01 FLTB RESET
1 1 1 0→1 1 0
0
V
SG
<V<V
OL
L Z→L L 01 FLTB SET
1 1 1 1 1 0 0 < V
SG
L L L 10 FLAGS SET
1 1 1 X 1→0 0 0 < V
SG
L L L→Z 10 STAB RESET
1 1 1 X 0→1 0 0 < V
SG
L L Z→L 10 STAB SET
1 1 1 1→0 1 0 0 < V
SG
L L→Z L 10 FLTB RESET
1 1 1 0→1 1 0
0
< V
SG
L Z→L L 10 FLTB SET
1 1 1 X 1 1 X < V
FLTREF
H Z L 00 STAB SET
1 1 1 1 1 1 X V
FLTREF
<V<V
OL
L L L 11 FLAGS SET
1 1 1 X 1→0 1
X
V
FLTREF
<V<V
OL
L L L→Z
11
STAB RESET
1 1 1 X 0→1 1
X
V
FLTREF
<V<V
OL
L L Z→L
11
STAB SET
1 1 1 1→0 1 1
X
V
FLTREF
<V<V
OL
L L→Z L
11
FLTB RESET
1 1 1 0→1 1 1
X
V
FLTREF
<V<V
OL
L Z→L L
11
FLTB SET
1 1 1 1 1 1 X > V
OL
L L Z 11 STAB RESET
1 1 1 X 1 X 1 < V
FLTREF
H Z L 00 STAB SET
1 1 1 1 1 X 1 V
FLTREF
<V<V
OL
L L L 11 FLAGS SET
1 1 1 X 1→0 X 1 V
FLTREF
<V<V
OL
L L L→Z 11 STAB RESET
1 1 1 X 0→1 X 1 V
FLTREF
<V<V
OL
L L Z→L 11 STAB SET
1 1 1 1→0 1 X 1 V
FLTREF
<V<V
OL
L L→Z L 11 FLTB RESET
1 1 1 0→1 1 X 1 V
FLTREF
<V<V
OL
L Z→L L 11 FLTB SET
1 1 1 1 1 X 1 > V
OL
L L Z 11 STAB RESET
* Output states after blanking and filter timers end and when channel is set to latch−off mode.
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NCV7513BFTR2G

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Manufacturer:
ON Semiconductor
Description:
Gate Drivers HEX LO-SIDE PRE-Drvr
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