NCV7513B
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16
B
+
CMP2
I
OL
+
_
+
CMP1
V
CTR
V
OL
V
CC1
A
V
LOAD
(V
CL
)
50
DRN
X
R
DX
R
LOAD
R
SG
V
X
1600
I
SG
D1
D2
D3
D4
DZ1
V
SG
+V
OS
Figure 15. Short to GND/Open−Load Detection
When a channel is off and V
LOAD
and R
LOAD
are
present, R
SG
is absent, and V
DRNX
>> V
CTR
, bias current
I
OL
is supplied from V
LOAD
to ground through external
resistors R
LOAD
and R
DX
, and through the internal 1650 W
resistance and bridge diode D2. Bias current I
SG
is supplied
from V
CC1
to V
CTR
through D3. No fault is detected if the
feedback voltage (V
LOAD
minus the total voltage drop
caused by I
SG
and the resistance in the path) is greater than
V
OL
.
When either V
LOAD
or R
LOAD
and R
SG
are absent, the
bridge will self−bias so that the voltage at DRN
X
will settle
to about V
CTR
. An open load fault can be detected since the
feedback is between V
SG
and V
OL
.
Short to GND detection can tolerate up to a 1.0 V offset
(V
OS
) between the NCV7513B’s GND and the short. When
R
SG
is present and V
DRNX
<< V
CTR
, bias current I
SG
is
supplied from V
CC1
to V
OS
through D1, the internal
1650 W, and the external R
DX
and R
SG
resistances. Bias
current I
OL
is supplied from V
CTR
to ground through D4.
A “weak” short to GND can be detected when either
V
LOAD
or R
LOAD
is absent and the feedback (V
OS
plus the
total voltage rise caused by I
OL
and the resistance in the
path) is less than V
OL
.
When V
LOAD
and R
LOAD
are present, a voltage divider
between V
LOAD
and V
OS
is formed by R
LOAD
and R
SG
. A
“hard” short to GND may be detected in this case
depending on the ratio of R
LOAD
and R
SG
and the values of
R
DX
, V
LOAD
, and V
OS
.
Note that the comparators see a voltage drop or rise due
only to the 50 W internal resistance and the bias currents.
This produces a small difference in the comparison to the
actual feedback voltage at the DRN
X
input.
Several equations for choosing R
DX
and for predicting
open load or short to GND resistances, and a discussion of
the dynamic behavior of the short to GND/open load
diagnostic are provided in the Applications Information
section of this data sheet.
Status Flag (STAB)
The open−drain active−low status flag output can be used
to provide a host controller with information about the state
of a channel’s DRN
x
feedback. Feedback from all channels
is logically ORed to the flag (Figure 16). The STAB
outputs from several devices can be wire−ORed to a
common pullup resistor connected to the controllers 3.3 or
5.0 V V
DD
supply.
When ENA1 is high, the drain feedback from a channel’s
DRN
x
input is compared to the V
OL
reference without
regard to ENA2 or the commanded state of the channel’s
driver. The flag is reset and disabled when ENA1 is low or
when all mask bits are set. See Table 9 for additional
details.
The flag is set (low) when the feedback voltage is less
than V
OL
, and the channel’s mask bit (Table 5) is cleared.
The flag is reset (hi−Z) when the feedback voltage is
greater than V
OL
, and the channel’s mask bit is cleared.
+
CMP1
V
OL
A
DRN
X
K
X
ENA1
POR
OTHER
CHANNELS
500 kHz
STAB
D
Q
CLR
Figure 16. STAB Flag Logic
Fault Flag (FLTB)
The open−drain active−low fault flag output can be used
to provide immediate fault notification to a host controller.
Fault detection from all channels is logically ORed to the
flag (Figure 17). The FLTB outputs from several devices
can be wire−ORed to a common pullup resistor connected
to the controllers 3.3 or 5.0 V V
DD
supply.
The flag is set (low) when a channel detects any fault, the
channel’s mask bit (Table 5) is cleared, and both ENA
x
and
CSB are high. The flag is reset (hi−Z) and disabled when
either ENA1 or CSB is low. See Table 9 for additional
details.
K
X
OTHER
CHANNELS
S
Q
FLT
B
FAULT
X
R
POR
E
NA2
CSB
(RESET DOMINANT)
ENA1
Figure 17. FLTB Flag Logic
NCV7513B
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17
Fault Detection and Capture
Each channel of the NCV7513B is capable of detecting
shorted load faults when the channel is on, and short to
ground or open load faults when the channel is off. Each
fault type is uniquely encoded into two−bit per channel
fault data. A drain feedback input for each channel
compares the voltage at the drain of the channel’s external
MOSFET to several internal reference voltages. Separate
detection references are used to distinguish the three fault
types, and blanking and filter timers are used respectively
to allow for output state transition settling and for glitch
suppression.
Fault diagnostics are disabled when either enable input
is low. When both enable inputs are high, each channel’s
drain feedback input is continuously compared to
references appropriate to the channel’s input state to detect
faults, but the comparison result is only latched at the end
of either a blanking or filter timer event.
Blanking timers for all channels are triggered when
either enable input changes state from low to high while the
other enable input is high, or when both enable inputs go
high simultaneously. A single channel’s blanking timer is
triggered when its input state changes. If the comparison of
the feedback to a reference indicates an abnormal condition
when the blanking time ends, a fault has been detected and
the fault data is latched into the channel’s fault latch.
A channel’s filter timer is triggered when its drain
feedback comparison state changes. If the change indicates
an abnormal condition when the filter time ends, a fault has
been detected and the fault data is latched into the channel’s
fault latch.
Thus, a state change of the inputs (ENA
X
, IN
X
or G
X
) or
a state change of an individual channel’s feedback (DRN
X
)
comparison must occur for a timer to be triggered and a
detected fault to be captured.
Fault Capture, SPI Communication, and SPI
Frame Error Detection
The fault capture and frame error detection strategies of
the NCV7513B combine to ensure that intermittent faults
can be captured and identified, and that the device cannot
be inadvertently reprogrammed by a communication error.
The NCV7513B latches a fault when it is detected, and
frame error detection will not allow any register to accept
data if an invalid frame occurred.
When a fault has been detected, the FLTB flag is set and
fault data is latched into a channel’s fault latch. The latch
captures and holds the fault data and ignores subsequent
fault data for that channel until a valid SPI frame occurs.
Fault data from all channels is transferred from each
channel’s fault latch into the SPI shift register and the FLTB
flag is reset when CSB goes low at the start of the SPI
frame. Fault latches are cleared and re−armed when CSB
goes high at the end of the SPI frame only if a valid frame
has occurred; otherwise the latches retain the detected fault
data until a valid frame occurs. The FLTB flag will be set
if a fault is still present.
Fault latches for all channels and the FLTB flag can also
be cleared and re−armed by toggling ENA1 H−L−H. A full
I/O truth table is given in Table 9.
Fault Data Readback Examples
Several examples are shown to illustrate fault detection,
capture and SPI read−back of fault data for one channel. A
normal SPI frame returns 16 bits of data but only the two
bits of serial data for the single channel are shown for
clarity.
The examples assume:
The NCV7513B is configured as in Figure 2
Both enable inputs are high
The channel’s flag mask bit is cleared
Disable mode is set to auto−retry
The parallel input commands the channel
SPI frame is always valid
Shorted Load Detected
Refer to Figure 18. The channel is commanded on when
IN
X
goes high. GAT
X
goes high and the timers are started.
At “A”, the STAB flag is set as the DRN
X
feedback falls
through the V
OL
threshold. A SPI frame sent soon after the
IN
X
command returns data indicating “no fault.”
The blanking time ends and the filter timer is triggered
as DRN
X
rises through the FLTREF threshold. The STAB
flag is reset as DRN
X
passes through the V
OL
threshold.
DRN
X
is nearly at V
LOAD
when the filter time ends at “B”.
A shorted load fault is detected and captured by the fault
latch, GAT
X
goes low, the FLTB flag is set, and the
auto−retry timer is started.
An SPI frame sent soon after “B” returns data indicating
“shorted load”. The FLTB flag is reset when CSB goes low.
At “C” when CSB goes high at the end of the frame, the
fault latch is cleared and re−armed. Since IN
X
and the
DRN
X
feedback are unchanged, FLTB and the fault latch
are set and the fault is recaptured.
When the auto−retry timer ends at “D”, GAT
X
goes high
and the blanking and filter timers are started. Since IN
X
and
DRN
X
are unchanged, GAT
X
goes low when the blanking
time ends at “E” and the auto−retry timer is started.
Read−back data continues to indicate a “shorted load” and
the FLTB flag continues to be set while the fault persists.
NCV7513B
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18
0
1
1100 11
0
1
0
1
FAULT
LATCH
BLANK
TIMER
FILTER
TIMER
t
FF
t
BL(ON)
t
FR
t
BL(ON)
111111
DRNx
INx
0
1
FLTREF
0
VLOAD
VOL
SO
FLTB
0
1
0
1
CSB
0
1
11 11 11 11 11
GATx
0
1
STAB
0
1
B
E
A
INTERNAL
SIGNALS
C
00
FAULT DETECTED
D
t
FR
Figure 18. Shorted Load Detected

NCV7513BFTR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Gate Drivers HEX LO-SIDE PRE-Drvr
Lifecycle:
New from this manufacturer.
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