15
LTC1401
1401fa
TYPICAL APPLICATIONS
U
TMS320C50 Code for Circuit
THIS PROGRAM DEMONSTRATES THE LTC1401 INTERFACE TO THE
TMS320C50. FRAME SYNC PULSE IS GENERATED FROM TFSX.
DATA SHIFT CLOCK IS DERIVED FROM CLKOUT.
*Initialization*
.mmregs ; Defines global symbolic names
;- - Initialized data memory to zero
.ds 0F00h ; Initialize data to zero
DATA0 .word 0 ; Begin sample data location
DATA1 .word 0 ; .
DATA2 .word 0 ; Location of data
DATA3 .word 0 ; .
DATA4 .word 0 ; .
DATA5 .word 0 ; End sample data location
;- - Set up the ISR vector
.ps 080Ah ; Serial ports interrupts
rint : B RECEIVE ; 0A;
xint : B TRANSMIT ; 0C;
trnt : B TREC ; 0E;
txnt : B TTRANX ; 10;
;- - Setup the reset vector
.ps 0A00h
.entry
START:
*TMS320C50 Initialization*
SETC INTM ; Temporarily disable all interrupts
LDP #0 ; Set data page pointer to zero
OPL #0834h, PMST ; Set up the PMST status and control register
LACC #0
SAMM CWSR ; Set software wait state to 0
SAMM PDWSR ;
*Configure Serial Port*
SPLK #0028h, TSPC ; Set TDM Serial Port
; TDM = 0 Stand Alone mode
; DLB = 0 Not loop back
; FO = 0 16 Bits
; FSM = 1 Burst Mode
; MCM = 0 CLKR is generated externally
; TXM = 1 FSX as output pin
; Put serial port into reset
; (XRST = RRST = 0)
SPLK #00E8h, TSPC ; Take Serial Port out of reset
; (XRST = RRST = 1)
SPLK #0FFFFh, IFR ; Clear all the pending interrupts
*Start Serial Communication*
SACL TDXR ; Generate frame sync pulse
SPLK #040h, IMR ; Turn on TRNT receiver interrupt
CLRC INTM ; Enable interrupt
CLRC SXM ; For Unipolar input, set for right shift
; with no sign extension
MAR *AR7 ; Load the auxiliary register pointer with seven
LAR AR7, #0F00h ; Load the auxiliary register seven with #0F00h
; as the begin address for data storage
WAIT: NOP ; Wait for a receive interrupt
NOP ;
NOP ;
SACL TDXR ; !! Regenerate the frame sync pulse
B WAIT ;
; - - - - - - - end of main program - - - - - - - - - - ;
*Receiver Interrupt Service Routine*
TREC:
LAMM TRCV ; Load the data received from LTC1401
SFR ; Shift right two times
SFR ;
AND #1FFFh, 0 ; ANDed with #1FFFh
; For converting the data to right
; justified format
;
SACL *+, 0 ; Write to data memory pointed by AR7 and
; Increase the memory address by one
LACC AR7 ;
SUB #0F05h,0 ; Compare to end sample address #0F05h
BCND
END_TRCV, GEQ
; If the end sample address has exceeded jump
to END_TRCV
;
SPLK #040h, IMR ; Else re-enable the TRNT receive interrupt
RETE ; Return to main program and enable interrupt
*After Obtained the Data from LTC1401, Program Jump to END_TRCV*
END_TRCV:
SPLK #002h, IMR ; Enable INT2 for program to halt
CLRC INTM
SUCCESS:
B SUCCESS
*Fill the unused interrupt with RETE, to avoid program get “lost”*
TTRANX:
RETE
RECEIVE:
RETE
TRANSMIT:
RETE
INT2:
B halt ; Halts the running CPU
