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NCP5331FTR2

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25
For increasing current
t
INC
Lo I
O
(V
IN
V
CORE
)
(3.1)
For decreasing current
t
DEC
Lo I
O
(V
CORE
)
(3.2)
For typical processor applications with output voltages
less than half the input voltage, the current will be increased
much more quickly than it can be decreased. It may be more
difficult for the converter to stay within the regulation limits
when the load is removed than when it is applied − excessive
overshoot may result.
The output voltage ripple can be calculated using the
output inductor value derived in this Section (Lo
MIN
), the
number of output capacitors (N
OUT,MIN
) and the per
capacitor ESR determined in the previous Section.
V
OUT,P−P
(ESR per cap N
OUT,MIN
)
(V
IN
#Phases V
CORE
) D (Lo
MIN
f
SW
)
(4)
This formula assumes steady−state conditions with no
more than one phase on at any time. The second term in
Equation 4 is the total ripple current seen by the output
capacitors. The total output ripple current is the “time
summation” of the two individual phase currents that are
180 degrees out−of−phase. As the inductor current in one
phase ramps upward, current in the other phase ramps
downward and provides a canceling of currents during part
of the switching cycle. Therefore, the total output ripple
current and voltage are reduced in a multiphase converter.
3. Input Capacitor Selection
The choice and number of input capacitors is primarily
determined by their voltage and ripple current ratings. The
designer must choose capacitors that will support the worst
case input voltage with adequate margin. To calculate the
number of input capacitors one must first determine the total
rms input ripple current. To this end, begin by calculating the
average input current to the converter.
I
IN,AVG
I
O,MAX
D
(5)
where
D is the duty cycle of the converter,
D = V
CORE
/V
IN
,
η is the specified minimum efficiency,
I
O,MAX
is the maximum converter output current.
The input capacitors will discharge when the control FET
is ON and charge when the control FET is OFF as shown in
Figure 30.
The following equations will determine the maximum and
minimum currents delivered by the input capacitors.
I
C,MAX
I
Lo,MAX
I
IN,AVG
(6)
I
C,MIN
I
Lo,MIN
I
IN,AVG
(7)
I
Lo,MAX
is the maximum output inductor current.
I
Lo,MAX
I
O,MAX
2 I
Lo
2
(8)
I
C,MAX
I
C,MIN
0 A
−I
IN,AVG
FET On,
Caps Discharging
FET Off,
Caps Charging
t
ON
T/2
I
C,IN
= I
C,MAX
− I
C,MIN
Figure 30. Input Capacitor Current for a
Two−Phase Converter
I
Lo,MIN
is the minimum output inductor current.
I
Lo,MIN
I
O,MAX
2 I
Lo
2
(9)
I
Lo
is the peak−to−peak ripple current in the output
inductor of value L
o
.
I
Lo
(V
IN
V
CORE
) D(Lo f
SW
)
(10)
For the two−phase converter, the input capacitor(s) rms
current is then
I
CIN,RMS
[2D (I
C,MIN
2
I
C,MIN
I
C,IN
I
C,IN
2
3) I
IN,AVG
2
(1 2D)]
12
(11)
Select the number of input capacitors (N
IN
) to provide the
rms input current (I
CIN,RMS
) based on the rms ripple current
rating per capacitor (I
RMS,RATED
).
N
IN
I
CIN,RMS
I
RMS,RATED
(12)
For a two−phase converter with perfect efficiency (η = 1),
the worst case input ripple current will occur when the
converter is operating at a 25% duty cycle. At this operating
point, the parallel combination of input capacitors must
support an rms ripple current equal to 25% of the converter’s
dc output current. At other duty cycles, the ripple current
will be less. For example, at a duty cycle of either 10% or
40%, the two−phase input ripple current will be
approximately 20% of the converter’s dc output current.
In general, capacitor manufacturers require derating to the
specified ripple current based on the ambient temperature.
More capacitors will be required because of the current
derating. The designer should be cognizant of the ESR of the
input capacitors. The input capacitor power loss can be
calculated from
P
CIN
I
CIN,RMS
2
ESR_per_capacitorN
IN
(13)
Low ESR capacitors are recommended to minimize losses
and reduce capacitor heating. The life of an electrolytic
capacitor is reduced 50% for every 10°C rise in the
capacitor’s temperature.
NCP5331
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+ +
Vi
12 V
Li
TBD
Ci
5 × 16MBZ1500M10X20
ESR
Ci
13 m/5 = 2.6 m
Q2
Q1
Lo
729 nH
ESR
Co
19 m/6 = 3.2 m
26 u(t)
Co
6 × 16MBZ1000M10X16
Vi(t = 0) = 12 V SWNODE Vo(t = 0) = 1.225 V
V
Ci
I
Lo
V
OUT
I
Li
MAX dI/dt occurs in
first few PWM cycles.
Figure 31. Calculating the Input Inductance
+
−
4. Input Inductor Selection
The use of an inductor between the input capacitors and
the power source will accomplish two objectives. First, it
will isolate the voltage source and the system from the noise
generated in the switching supply. Second, it will limit the
inrush current into the input capacitors at power up. Large
inrush currents will reduce the expected life of the input
capacitors. The inductor’s limiting effect on the input
current slew rate becomes increasingly beneficial during
load transients.
The worst case input current slew rate will occur during
the first few PWM cycles immediately after a step−load
change is applied as shown in Figure 31. When the load is
applied, the output voltage is pulled down very quickly.
Current through the output inductors will not change
instantaneously so the initial transient load current must be
conducted by the output capacitors. The output voltage will
step downward depending on the magnitude of the output
current (I
O,MAX
), the per capacitor ESR of the output
capacitors (ESR
OUT
), and the number of the output
capacitors (N
OUT
) as shown in Figure 31. Assuming the load
current is shared equally between the two phases, the output
voltage at full, transient load will be
V
CORE,FULL−LOAD
(14)
V
CORE,NO−LOAD
(I
O,MAX
2) ESR
OUT
N
OUT
When the control MOSFET (Q1 in Figure 31) turns ON,
the input voltage will be applied to the opposite terminal of
the output inductor (the SWNODE). At that instant, the
voltage across the output inductor can be calculated as
V
Lo
V
IN
V
CORE,FULL−LOAD
(15)
V
IN
V
CORE,NO−LOAD
(I
O,MAX
2) ESR
OUT
N
OUT
The differential voltage across the output inductor will
cause its current to increase linearly with time. The slew rate
of this current can be calculated from
dI
Lo
dt V
Lo
Lo
(16)
Current changes slowly in the input inductor so the input
capacitors must initially deliver the vast majority of the
input current. The amount of voltage drop across the input
capacitors (V
Ci
) is determined by the number of input
capacitors (N
IN
), their per capacitor ESR (ESR
IN
), and the
current in the output inductor according to
V
Ci
ESR
IN
N
IN
dI
Lo
dt t
ON
ESR
IN
N
IN
dI
Lo
dt Df
SW
(17)
Before the load is applied, the voltage across the input
inductor (V
Li
) is very small − the input capacitors charge to
the input voltage, V
IN
. After the load is applied the voltage
drop across the input capacitors, V
Ci
, appears across the
input inductor as well. Knowing this, the minimum value of
the input inductor can be calculated from
Li
MIN
V
Li
dI
IN
dt
MAX
V
Ci
dI
IN
dt
MAX
(18)
where dI
IN
/dt
MAX
is the maximum allowable input current
slew rate.
The input inductance value calculated from Equation 18
is relatively conservative. It assumes the supply voltage is
very “stiff” and does not account for any parasitic elements
that will limit dI/dt such as stray inductance. Also, the ESR
values of the capacitors specified by the manufacturer’s data
sheets are worst case high limits. In reality input voltage
“sag,” lower capacitor ESRs, and stray inductance will help
reduce the slew rate of the input current.
As with the output inductor, the input inductor must
support the maximum current without saturating the
magnetic. Also, for an inexpensive iron powder core, such
as the −26 or −52 from Micrometals, the inductance “swing”
with dc bias must be taken into account − inductance will
decrease as the dc input current increases. At the maximum
input current, the inductance must not decrease below the
minimum value or the dI/dt will be higher than expected.
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5. MOSFET and Heatsink Selection
Power dissipation, package size, and thermal solution drive
MOSFET selection. To adequately size the heat sink, the
design must first predict the MOSFET power dissipation.
Once the dissipation is known, the heat sink thermal
impedance can be calculated to prevent the specified
maximum case or junction temperatures from being exceeded
at the highest ambient temperature. Power dissipation has two
primary contributors: conduction losses and switching losses.
The control or upper MOSFET will display both switching
and conduction losses. The synchronous or lower MOSFET
will exhibit only conduction losses because it switches into
nearly zero voltage. However, the body diode in the
synchronous MOSFET will suffer diode losses during the
nonoverlap time of the gate drivers.
For the upper or control MOSFET, the power dissipation
can be approximated from
P
D,CONTROL
(I
RMS,CNTL
2
R
DS(on)
)
(I
Lo,MAX
Q
switch
I
g
V
IN
f
SW
)
(Q
oss
2 V
IN
f
SW
) (V
IN
Q
RR
f
SW
)
(19)
The first term represents the conduction or IR losses when
the MOSFET is ON, while the second term represents the
switching losses. The third term is the losses associated with
the control and synchronous MOSFET output charge when
the control MOSFET turns ON. The output losses are caused
by both the control and synchronous MOSFET but are
dissipated only in the control FET. The fourth term is the loss
due to the reverse recovery time of the body diode in the
synchronous MOSFET. The first two terms are usually
adequate to predict the majority of the losses.
I
RMS,CNTL
is the rms value of the trapezoidal current in the
control MOSFET.
(20)
I
RMS,CNTL
[D (I
Lo,MAX
2
I
Lo,MAX
I
Lo,MIN
I
Lo,MIN
2
)3]
12
I
Lo,MAX
is the maximum output inductor current.
I
Lo,MAX
I
O,MAX
2 I
Lo
2
(21)
I
Lo,MIN
is the minimum output inductor current.
I
Lo,MIN
I
O,MAX
2 I
Lo
2
(22)
I
O,MAX
is the maximum converter output current.
D is the duty cycle of the converter.
D V
CORE
V
IN
(23)
I
Lo
is the peak−to−peak ripple current in the output
inductor of value L
o
.
I
Lo
(V
IN
V
CORE
) D(Lo f
SW
)
(24)
R
DS(on)
is the ON resistance of the MOSFET at the
applied gate drive voltage.
Q
switch
is the post gate threshold portion of the
gate−to−source charge plus the gate−to−drain charge. This
may be specified in the data sheet or approximated from the
gate−charge curve as shown in the Figure 32.
I
D
V
GATE
V
DRAIN
Q
GD
Q
GS2
Q
GS1
V
GS_TH
Figure 32. MOSFET Switching Characteristics
Q
switch
Q
gs2
Q
gd
(25)
I
g
is the output current from the gate driver IC.
V
IN
is the input voltage to the converter.
f
sw
is the switching frequency of the converter.
Q
RR
is the reverse recovery charge of the lower MOSFET.
Q
oss
is the sum of all the MOSFET output charges.
For the lower or synchronous MOSFET, the power
dissipation can be approximated from
P
D,SYNCH
(I
RMS,SYNCH
2
R
DS(on)
)
(Vf
diode
I
O,MAX
2 t_nonoverlap f
SW
)
(26)
The first term represents the conduction or IR losses when
the MOSFET is ON, and the second term represents the
diode losses that occur during the gate nonoverlap time.
All terms were defined in the previous discussion for the
control MOSFET with the exception of
(27)
I
RMS,SYNCH
[(1 D)
(I
Lo,MAX
2
I
Lo,MAX
I
Lo,MIN
I
Lo,MIN
2
)3]
12
Vf
diode
is the forward voltage of the MOSFET’s intrinsic
diode at the converter output current.
t_nonoverlap is the nonoverlap time between the upper
and lower gate drivers to prevent cross conduction. This
time is usually specified in the data sheet for the control IC.
When the MOSFET power dissipations are known, the
designer can calculate the required thermal impedance to
maintain a specified junction temperature at the worst case
ambient operating temperature.
T
(T
J
T
A
)P
D
(28)
where
T
is the total thermal impedance (
JC
+
SA
),
JC
is the junction−to−case thermal impedance of
the MOSFET,
SA
is the sink−to−ambient thermal impedance of
the heatsink assuming direct mounting of the
MOSFET (no thermal “pad” is used),
T
J
is the specified maximum allowed junction
temperature,
T
A
is the worst case ambient operating temperature.
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NCP5331FTR2

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