NCP5331
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34
Equation 28 is used to calculate the heat sink thermal
impedances necessary to maintain less than the specified
maximum junction temperatures at 55°C ambient.
CNTRL
SA
(120 55°C)1.48 W 1.65°CW
42.3°CW
SYNCH
SA
(120 55°C)0.85 W 1.65°CW
74.8°CW per MOSFET
or 37.4°CW per phase for two MOSFETsphase
If board area permits, a cost effective heatsink could be
formed by using a TO−263 mounting pad of at least 2.0 in
2
(1282 mm
2
) for the upper and lower MOSFETs on a
single−sided, 1 oz copper PCB. The total required pad area
would be slightly less if the area were divided evenly
between top and bottom layers with multiple thermal vias
joining the two areas. To conserve board space, AAVID
offers clip−on heatsinks for TO−220 thru−hole packages.
Examples of these heatsinks include #577002 (1″×0.75 ×
0.25, 33°C/W at 2 W) and #591302 (0.75″×0.5″×0.5,
29°C/W at 2 W).
6. Adaptive Voltage Positioning
First, to achieve the 200 kHz switching frequency, use
Figure 5 to determine that a 51 k resistor is needed for
R
OSC
. Then, use Figure 6 to find the V
FB
bias current at the
corresponding value of R
OSC
. In this example, the 51 k
R
OSC
resistor results in a V
FB
bias current of approximately
7.0 A. Knowing the V
FB
bias current, one can calculate the
required values for R
F1
and R
DRP
using Equation 29 through
Equation 31.
The no−load position is easily set using Equation 29.
R
VFBK
V
NO−LOAD
IBIAS
VFB
+25 mV7.0 A
3.6 k
(29)
For inductive current sensing, the designer must calculate
the inductors resistance (R
L
) and approximate any
resistance added by the circuit board (R
PCB
). We found the
inductors nominal resistance in Section 2 (0.965 m). In
this example, we assume 0.2 m for the circuit board
resistance (R
PCB
). With this information, Equation 30 can
be used to calculate the increase at the V
DRP
pin at full load.
V
DRP
I
O,MAX
(R
L
R
PCB
) G
VDRP
52 A (0.965 m 0.2 m) 4.2 VV
0.254 mV
(30)
R
DRP
can then be calculated from Equation 31.
R
DRP
V
DRP
(IBIAS
VFB
V
CORE,FULL−LOAD
R
F1
)
(31)
254 mV(7.0 A 37 mV3.6 k)
14.7 k
7. Current Sensing
Choose the current sense network (R
Sx
, C
Sx
, x = 1 or 2) to
satisfy
R
Sx
C
Sx
Lo(R
L
R
PCB
)
(32)
Equation 32 will be most accurate for better iron powder
core material (such as the −8 from Micrometals). This
material is very consistent with dc current and frequency.
Less expensive core materials (such as the −52 from
Micrometals) change their characteristics with dc current,
ac flux density, and frequency. This material will yield
acceptable converter performance if the current sense time
constant is set lower (longer) than anticipated. As a rule of
thumb, start with approximately twice the resistance (R
Sx
)
or twice the capacitance (C
Sx
) when using the less expensive
core material.
The component values determined thus far are L
o
= 828 nH,
R
L
= 0.965 m, and R
PCB
= 0.2 m. We choose a convenient
value for C
S1
(0.1 F) and solve for R
Sx
.
R
Sn
828 nH(0.965 m 0.2 m) 0.1 F
7.10 k
After the circuit is constructed, the values of R
Sx
and/or
C
Sx
should be tuned to provide a “square−wave” at the V
DRP
pin with minimal overshoot and fast rise time due to a step
change in load current as shown in Figure 35, Figure 36 and
Figure 37. This testing has shown that for a 3 to 25 A
transient, a value of 10.0 k will produce the desired square
wave at V
DRP.
8. Error Amplifier Tuning
The error amplifier is tuned by adjusting C
A1
to provide
an acceptable full−load transient response as shown in
Figure 38, Figure 39 and Figure 40. After a value for C
A1
is
chosen, the peak−to−peak voltage ripple on the COMP pin
is examined under full−load to insure less than 20 mVpp as
shown in Figure 41.
9. Current Limit Setting
The maximum inductor resistance, the maximum PCB
resistance, and the maximum current−sense gain determine
the current limit as shown in Equation 34. The maximum
current, I
OUT,LIMIT
, was specified in the design
requirements. The maximum inductor resistance occurs at
full load and the highest ambient temperature. This value
was found in the “Output Inductor Section” (1.28 m). This
analysis assumes the PCB resistance only increases due to
the change in ambient temperature. Component heating will
also increase the PCB temperature but quantifying this
effect is difficult. Lab testing should be used to “fine tune”
the overcurrent threshold.
R
PCB,MAX
0.2 m {1 0.39%°C
(100°C 25°C)}
0.26 m
NCP5331
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35
V
ILIM
(I
OUT,LIM
I
Lo
2) (R
LMAX
R
PCB,MAX
)
G
ILIM
(72 A 7.20 A2) (1.28 m 0.26 m)
12 VV
1.4 Vdc
Set the voltage at the I
LIM
pin using a resistor divider from
the 5.0 V reference output as shown in Figure 42. If the
resistor from I
LIM
to GND is chosen to be 910 (R
LIM2
),
then the resistor from I
LIM
to 5.0 V
REF
can be calculated
from
R
LIM1
(V
REF
V
ILIM
)(V
ILIM
R
LIM2
)
(5.0 V 1.4 V)(1.4 V910 )
2340 or 2.37 k
10. Overcurrent Timer
To set the overcurrent timer, solve Equation 35 for C
OVC
and substitute t
OVC
= 120 ms.
C
OVC
t
OVC
(5.5 10
5
)
(35)
120 ms(5.5 10
5
)
0.218 For0.22 F
11. Soft Start Time
To set the Soft Start time, first calculate the external ramp
size at a duty−cycle of D = 1.225 V/12 V = 0.102.
Ext_Ramp D
(V
IN
V
OUT
)
(R
Sx
C
Sx
f
SW
)
0.102
(12 V 1.225 V)
(10.0 k 0.1 F 200 kHz)
5.5 mV
R
LIM2
910
R
LIM1
5 V
REF
To I
LIM
Pin
V
LIM
Figure 42. Setting the Current Limit
Then calculate the steady−state COMP voltage.
V
COMP
V
OUT
@0A Channel_Startup_Offset
Int_Ramp G
CSA
Ext_Ramp2
1.225 V 0.60 V 0.102 250 mV
4.0 VV 5.3 mV2
1.86 V
Finally, solve Equation 35 for the soft−start capacitor,
C
C2
, and substitute as required.
C
C2
(t
SS
I
COMP
)(V
COMP
R
C1
I
COMP
)
(36)
(6 ms 30 A)(1.86 V 7.5 k 30 A)
0.11 For0.1 F
12. Power Good Delay Time
First, use the previously derived value for R
OSC
to
calculate the current that will be supplied to the C
PGD
capacitor.
I
PGD
0.52 VR
OSC
0.52 V51 k
10.2 A
Next, solve equation 37 for C
PGD
and substitute as
required.
C
PGD
t
PGD
I
PGD
(PGD
THRESH
PGD
MIN
)
(37)
6ms 10.2 A(3.0 V 0.25 V)
0.022 F
NCP5331
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36
PACKAGE DIMENSIONS
LQFP−32
FT SUFFIX
CASE 873A−02
ISSUE B
DETAIL Y
A
S1
VB
1
8
9
17
25
32
AE
AE
P
DETAIL Y
BASE
N
J
DF
METAL
SECTION AE−AE
G
SEATING
PLANE
R
Q
W
K
X
0.250 (0.010)
GAUGE PLANE
E
C
H
DETAIL AD
DETAIL AD
A1
B1
V1
4X
S
4X
9
−T−
−Z−
−U−
T−U0.20 (0.008) Z
AC
T−U0.20 (0.008) ZAB
0.10 (0.004) AC
−AC−
−AB−
M
8X
−T−, −U−, −Z−
T−U
M
0.20 (0.008) ZAC
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DATUM PLANE −AB− IS LOCATED AT
BOTTOM OF LEAD AND IS COINCIDENT
WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE
DETERMINED AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE
MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL NOT CAUSE THE
D DIMENSION TO EXCEED 0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY
VARY FROM DEPICTION.
DIM
A
MIN MAX MIN MAX
INCHES
7.000 BSC 0.276 BSC
MILLIMETERS
B 7.000 BSC 0.276 BSC
C 1.400 1.600 0.055 0.063
D 0.300 0.450 0.012 0.018
E 1.350 1.450 0.053 0.057
F 0.300 0.400 0.012 0.016
G 0.800 BSC 0.031 BSC
H 0.050 0.150 0.002 0.006
J 0.090 0.200 0.004 0.008
K 0.500 0.700 0.020 0.028
M 12 REF 12 REF
N 0.090 0.160 0.004 0.006
P 0.400 BSC 0.016 BSC
Q 1 5 1 5
R 0.150 0.250 0.006 0.010
V 9.000 BSC 0.354 BSC
V1 4.500 BSC 0.177 BSC


B1 3.500 BSC 0.138 BSC
A1 3.500 BSC 0.138 BSC
S 9.000 BSC 0.354 BSC
S1 4.500 BSC 0.177 BSC
W 0.200 REF 0.008 REF
X 1.000 REF 0.039 REF
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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V
2
is a trademark of Switch Power, Inc.
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IC REG CTRLR AMD 2OUT 32LQFP
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