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31
the inductors resistance increase due to current heating and
ambient temperature rise. Also, depending on the current
sense points, the circuit board may add additional resistance.
In general, the temperature coefficient of copper is +0.393%
per °C. If using a current sense resistor (R
SENSE
), the I
LIM
pin voltage should be set based on the maximum value of the
sense resistor. To set the level of the I
LIM
pin,
V
ILIM
(I
OUT,LIM
I
Lo
2) R G
ILIM
(34)
where
I
OUT,LIM
is the current limit threshold of the converter,
I
Lo
/2 is half the inductor ripple current,
R is either (R
LMAX
+ R
PCB
) or R
SENSE
,
G
ILIM
is the current sense to I
LIM
gain.
For the overcurrent protection to work properly, the
current sense time constant (RC) should be slightly larger
than the RL time constant. If the RC time constant is too fast,
during step load changes the sensed current waveform will
appear larger than the actual inductor current and will
probably trip the current limit at a lower level than expected.
10. Overcurrent Timer
The overcurrent timer sets the time the converter will
allow hiccup mode operation. Given the capacitance from
the C
OVC
pin to GND, the nominal overcurrent time (t
OVC
)
can be calculated from the following equation.
t
OVC
C
OVC
(OVC
THRESH
OVC
MIN
)I
OVC
(35)
C
OVC
(3.0 V 0.25 V)5.0 A
C
OVC
5.5 10
5
where
OVC
THRESH
is the overcurrent timers shutdown
voltage, nominally 3 V,
OVC
MIN
is the overcurrent timers starting
voltage, nominally 0.25 V,
I
OVC
is the charge current supplied to the
capacitor at the C
OVC
pin, nominally
5 A.
11. Soft Start Time
The Soft Start time (t
SS
) can be calculated from
t
SS
(V
COMP
R
C1
I
COMP
) C
C2
I
COMP
(36)
where
V
COMP
V
CORE
@0A Channel_Startup_Offset
Int_Ramp G
CSA
Ext_Ramp2
Ext_Ramp D (V
IN
V
CORE
)(R
CSx
C
CSx
f
SW
)
Int_Ramp 125 mV D0.50
I
COMP
is the COMP source current from the
data sheet,
Int_Ramp is the internal ramp value at the
corresponding duty cycle,
Ext_Ramp is the peak−to−peak external
steady−state ramp at 0 A,
G
CSA
is the Current Sense Amplifier Gain
(nominally 2.0 V/V),
Startup Offset is typically 0.60V.
12. Power Good Delay Time
The power good timer sets the delay time between when
V
CORE
exceeds the C
PGD
comparators threshold voltage
and when PGD will actually transition high. The PGD delay
time can be calculated from
t
PGD
C
PGD
(PGD
THRESH
PGD
MIN
)I
PGD
(37)
C
PGD
(3.0 V 0.25V)I
PGD
where
PGD
THRESH
is the PGD comparators threshold
voltage, nominally 3 V,
PGD
MIN
is the PGD timers starting voltage,
nominally 0.25 V,
I
PGD
is the charge current supplied to the
capacitor at the C
PGD
pin. This current
is a function of the R
OSC
resistor
according to I
PGD
= 0.52 V/R
OSC
.
Design Example
Typical Design Requirements:
V
IN
= 12.0 Vdc
V
CORE
= 1.20 Vdc (nominal)
V
OUT,RIPPLE
< 20 mV
PP
max
VID Range: 0.800 Vdc − 1.550 Vdc
I
O,MAX
= 52 A at full−load
I
OUT,LIM
= 72 Adc
dI
IN
/dt = 0.50 A/s max
f
SW
= 200 kHz
η = 80% min at full−load
T
A,MAX
= 55°C
T
J,MAX
= 120°C
t
SS
= 6.0 ms (Soft Start time)
t
OVC
= 120 ms (Overcurrent time)
t
PGD
= 6.0 ms (PGD Delay time)
V
CORE
at no−load (static) =
−25 mV from VID setting = 1.225 Vdc
V
CORE
at full−load (static) =
–37 mV from VID setting = 1.163 Vdc
V
CORE
transient loading from 3.0 A to 25 A =
−50 mV from VID setting = 1.150 Vdc
1. Output Capacitor Selection
First, choose a low−cost, low−ESR output capacitor such
as the Rubycon 16MBZ1000M10X16: 16 V, 1000 F,
2.55 A
RMS
, 19 m, 10 × 16 mm. Calculate the minimum
number of output capacitors.
N
OUT,MIN
ESR per capacitor
I
O,MAX
V
O,MAX
19 m 22 A(1.225 V 1.150 V)
5.6 or 6 capacitors minimum (6000 F)
(1)
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32
2. Output Inductor Selection
Calculate the minimum output inductance at I
O,MAX
according to Equation 3 with ±20% inductor ripple current
(α = 0.15).
Lo
MIN
(V
IN
V
OUT
) V
OUT
( I
O,MAX
V
IN
f
SW
)
(12 V 1.163 V) 1.163 V
(0.15 52 A 12 V 200 kHz)
673 nH
(3)
To minimize core losses, we choose the T508B/90 core
from Micrometals: 23.0 nH/N
2
, 2.50 cm/turn. According to
the Micrometals catalog, at 26 A (per phase) the
permeability of this core will be approximately 88% of the
permeability at 0 A. Therefore, at 0 A we must achieve at
least 673 nH/0.88 or 765 nH. Using 6 turns of #16 AWG
bifilar (2 m/ft) will produce 828 nH.
We will need the nominal and worst case inductor
resistances for subsequent calculations.
R
L
6 turns 2.5 cmturn 0.03218 ftcm 2mft
0.965 m
The inductor resistance will be maximized when the
inductor is “hot” due to the load current and the ambient
temperature is high. Assuming a 50°C temperature rise of
the inductor at full−load and a 35°C ambient temperature
rise we can calculate
R
L,MAX
0.965 m [1 0.39%°C (50°C 35°C)]
1.28 m
The output inductance at full−load will be reduced due to
the saturation characteristic of the core material.
Lo
52 A
0.88 828 nH 729 nH at full load
Next, use Equation 4 to insure the output voltage ripple
will satisfy the design goal with the minimum number of
output capacitors and the full load output inductance.
(1.163 V12 V)(729 nH 200 kHz)}
(4)
(19 m6) {(12 V 2 1.163 V)
20 mV
V
OUT,P−P
(ESR per cap N
OUT,MIN
)
{(V
IN
#Phases V
CORE
) D (Lo
52 A
f
SW
)}
So, the ripple requirement will be satisfied if the minimum
number of output capacitors is used. More output capacitors
will probably be required to satisfy the transient
requirement, which will result in a lower ripple voltage.
3. Input Capacitor Selection
Use Equation 5 to determine the average input current to
the converter at full−load.
I
IN,AVG
I
O,MAX
D
52 A (1.163 V12 V)0.80 6.30 A
(5)
Next, use Equation 6 to Equation 10 with the full−load
inductance value of 729 nH.
I
Lo
(V
IN
V
OUT
) D(Lo f
SW
)
(12 V 1.163 V)
(1.163 V12 V)
(729 nH 200 kHz)
7.20 App
(10)
I
Lo,MAX
I
O,MAX
2 I
Lo
2
52 A2 7.20 App2 29.6 A
(8)
I
Lo,MIN
I
O,MAX
2 I
Lo
2
52 A2 7.20 App2 22.4 A
(9)
I
C,MAX
I
Lo,MAX
I
IN,AVG
29.6 A0.80 6.30 A 30.7 A
(6)
I
C,MIN
I
Lo,MIN
I
IN,AVG
22.4 A0.80 6.30 A 21.7 A
(7)
For the two−phase converter, the input capacitor(s) rms
current at full−load is as follows. (Note: D = 1.163 V/12 V
= 0.097.)
I
CIN,RMS
[2D (I
C,MIN
2
I
C,MIN
I
C,IN
(11)
I
C,IN
2
3) I
IN,AVG
2
(1 2D)]
12
[0.19 (21.7
2
21.7 9.0 9.0
2
3)
6.30
2
(1 0.19)]
12
12.9 A
RMS
At this point, the designer must decide between saving
board space by using higher−rated/more costly capacitors
or saving cost by using more lower−rated/less costly
capacitors. To save cost, we choose the MBZ series
capacitors by Rubycon. Part number 16MBZ1500M10X20:
1500 F, 16 V, 2.55 A
RMS
, 13 m, 10 × 20 mm. This design
will require N
IN
= 12.8 A/2.55 A = 5 capacitors on the input
for a cost sensitive design or 6 capacitors for a conservative
design.
4. Input Inductor Selection
For the Claw Hammper CPU, the input inductor must
limit the input current slew rate to less than 0.5 A/s during
a load transient from 0 to 52 A. A conservative value will be
calculated assuming the minimum number of output
capacitors (N
OUT
= 6), five input capacitors (N
IN
= 5), worst
case ESR values for both the input and output capacitors,
and a maximum duty cycle at the maximum DAC setting
with 25 mV of no−load AVP.
D
MAX
(1.550 V 25 mV
AVP
)10.8 V
IN
0.146
NCP5331
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33
First, use Equation 15 to calculate the voltage across the
output inductor due to the 52 A load current being shared
equally between the two phases.
(15)
V
Lo
V
IN
V
CORE,NO−LOAD
(I
O,MAX
2) ESR
OUT
N
OUT
12 V 1.575 V 52 A2 19 m6
10.51 V
Second, use Equation 16 to determine the rate of current
increase in the output inductor when the load is applied (i.e.,
Lo has decreased to 88% due to the dc current).
dI
Lo
dt
V
Lo
Lo
10.51 V729 nH 14.4 Vs
(16)
Finally, use Equation 17 and Equation 18 to calculate the
minimum input inductance value.
V
Ci
ESR
IN
N
IN
dI
Lo
dt Df
SW
13 m5 14.4 Vs 0.146200 kHz
28 mV
(17)
Li
MIN
V
Ci
dI
IN
dt
MAX
28 mV0.50 As 55 nH
(18)
Next, choose the small, cost effective T30−26 core from
Micrometals (33.5 nH/N
2
) with #16 AWG. The design
requires only 1.28 turns to achieve the minimum inductance
value. We allow for inductance “swing” at full−load by
using three turns. The input inductors value will be
L
i
3
2
33.5 nHN
2
301 nH
This inductor is available as part number CTX15−14771
from Coiltronics.
5. MOSFET & Heatsink Selection
For the upper MOSFET we choose two (1) NTD60N03
and for the lower MOSFETs we choose two (2) NTD80N02,
both are from ON Semiconductor. The following parameters
are derived from the data sheets.
NCP5331 Parameter Value
Gate Drive Current 1.5 A for 1.0 s
Upper Gate Voltage 6.5 V
Lower Gate Voltage 11.5 V
Gate Nonoverlap Time 65 ns
Parameter NTD60N03 NTD80N02
R
DS(on)
8.0 m @ 6.5 V 5.0 m @ 10 V
Q
SWITCH
27 nC 26 nC
Q
RR
43 nC 36 nC
Q
OSS
12 nC 12 nC
V
F,diode
0.75 V @ 2.3 A 0.92 V @ 20 A
JC
1.65°C/W 1.65°C/W
The rms value of the current in the control MOSFET is
calculated from Equation 20 and the previously derived
values for D, I
LMAX
, and I
LMIN
at the converters maximum
output current.
0.097 [(29.6
2
29.6 22.4 22.4
2
)3]
12
(20)
I
RMS,CNTL
[D (I
Lo,MAX
2
I
Lo,MAX
I
Lo,MIN
I
Lo,MIN
2
)3]
12
2.53 A
RMS
Equation 19 is used to calculate the power dissipation of
the control MOSFET but has been modified for one upper
and two lower MOSFETs.
P
D,CONTROL
{
(I
RMS,CNTL
2
) R
DS(on)
}
(I
Lo,MAX
Q
switch
I
g
V
IN
f
SW
)
(3 Q
oss
2 V
IN
f
SW
) (V
IN
Q
RR
f
SW
)
(19)
{
2.53
2
A
RMS
8.0 m
}
(29.6 A 27 nC1.5 A 12 V 200 kHz)
(3 12 nC2 12 V 200 kHz)
(12 V 43 nC 200 kHz)
0.051 W 1.28 W 0.043 W 0.10 W
1.48 W per FET
The rms value of the current in the synchronous MOSFET
is calculated from Equation 27 and the previously derived
values for D, I
Lo,MAX
, and I
Lo,MIN
at the converters
maximum output current.
(27)
I
RMS,SYNCH
[(1 D)
(I
Lo,MAX
2
I
Lo,MAX
I
Lo,MIN
I
Lo,MIN
2
)3]
12
(1 0.097) [(29.6
2
29.6 22.4 22.4
2
)3]
12
23.5 A
RM
S
(shared by two synchronous MOSFETs)
Equation 26 is used to calculate the power dissipation of
each synchronous MOSFET. Note: The rms current is
shared by the two lower MOSFETs so the total rms current
is divided by two in the following equation. Also, during the
nonoverlap time, the per−phase current is shared by two
body diodes so the full load current is divided between two
phases and two forward body diodes per phase.
P
D,SYNCH
(I
RMS,SYNCH
2
R
DS(on)
)
(Vf
diode
I
O,MAX
2 t_nonoverlap f
SW
)
(26)
(23.52)
2
A
RMS
5.0 m
0.92 V (52 A22) 65 ns 200 kHz
0.69 W 0.16 W 0.85 W per FET

NCP5331FTR2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC REG CTRLR AMD 2OUT 32LQFP
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