NCP5331
http://onsemi.com
9
PACKAGE PIN DESCRIPTION
Pin No. Symbol Description
1 V
FB
Voltage Feedback Pin. To use Adaptive Voltage Positioning (AVP), set the light load offset voltage
by connecting a resistor between V
FB
and V
CORE
. The resistor and the V
FB
bias current determine
the offset. For no adaptive positioning connect V
FB
directly to V
CORE
.
2 V
DRP
Current sense output for Adaptive Voltage Positioning (AVP). The offset of this pin above the DAC
voltage is proportional to the output current. Connect a resistor from this pin to V
FB
to set the
amount AVP or leave this pin open for no AVP. This pin’s maximum working voltage is 4.1 Vdc.
3 LGND Return for the internal control circuits and the IC substrate connection.
4, 6 CS1, CS2 Current sense inputs. Connect the current sense network for the corresponding phase to each in-
put. The input voltages to these pins must be kept within 125 mV of CS
REF
.
5 CS
REF
Reference for both differential current sense amplifiers. To balance input offset voltages between
the inverting and non−inverting inputs of the Current Sense Amplifiers, connect this pin to the output
voltage through a resistor equal to one third of the value of the current sense resistors.
7 V
FFB
Fast Feedback connection to the PWM comparators and input to the Power Good comparator.
8 5 V
REF
Reference output. Decouple to LGND with 0.1 F.
9 R
OSC
A resistor from this pin to ground sets the operating frequency and V
FB
bias current.
10 −SEN Ground connection for the DAC. Provides remote sensing of ground at the load.
11−15 VID pins Voltage ID DAC inputs. These pins are internally pulled up and clamped at 2.3 V if left unconnected.
16 V
CCL2
Power for GL2.
17 GL2 Low side driver #2.
18 GND2 Return for driver #2.
19 GH2 High side driver #2.
20 V
CCH
Power for GH1 and GH2.
21 CB
OUT
Open−collector crowbar output pin. This pin is high impedance when an overvoltage condition is
detected at CS
REF
. Connect this pin to the gate of a MOSFET or SCR to crowbar either V
CORE
or
V
IN
to GND. To prevent failure of the crowbar device, this pin should be used in conjunction with
logic on the motherboard to disable the ATX supply via PS
ON
and/or a relatively fast fuse should be
placed upstream to disconnect the input voltage.
22 GH1 High side driver #1.
23 GND1 Return for driver #1.
24 GL1 Low side driver #1.
25 V
CCL1
Power for GL1.
26 V
CCL
Power for the internal control circuits. UVLO sense for Logic connects to this pin.
27 C
OVC
A capacitor from this pin to ground sets the time the controller will be in hiccup mode current limit.
This timer is started by the first overcurrent condition (set by the I
LIM
voltage). Once timed out, volt-
age at the V
CCL
pin must be cycled to reset this fault. Connecting this pin to LGND ±200 mV will
disable this function and hiccup mode current limit will operate indefinitely.
28 C
PGD
A capacitor from this pin to ground sets the programmable time between when V
CORE
crosses the
PWRGD threshold and when the open−collector PWRGD pin transitions from a logic Low to a logic
High. The minimum delay is internally set to 200 s. Connecting this pin to 5 V
REF
will disable the
programmable timer and the delay will be set to the internal delay.
29 PGD Power Good output. Open collector output that will transition Low when CS
REF
(V
CORE
) is out of
regulation.
30 5 V
SB
Input power for the CB
OUT
circuitry. To provide maximum overvoltage protection to the CPU, this pin
should be connected to 5 V
SB
from the ATX supply (ATX, pin 9). If the CB
OUT
function is not used,
this pin must be connected to the NCP5331 controller’s internal voltage reference (5 V
REF
, pin 8).
31 I
LIM
Sets the threshold for current limit. Connect to reference through a resistive divider. This pin’s maxi-
mum working voltage is 3.0 Vdc.
32 COMP Output of the error amplifier and input for the PWM comparators.
