ADF4360-0BCPZRL Datasheet ADF4360-0BCPZ, ADF4360-0BCPZRL7, ADF4360-0BCPZRL | P13-P15

ADF4360-0 Data Sheet

Rev. D | Page 12 of 24

LATCH STRUCTURE

Table 6 shows the three on-chip latches for the ADF4360-0. The two LSBs determine which latch is programmed.

Table 6. Latch Structure

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13

DB12 DB11

DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (0) C1 (0)

PC1PC2CRM1M2PDPCPCPG

MTLDPL1

PL2CPI1CPI2CPI3CPI4CPI5CPI6PD1 M3

CONTROL

BITS

MUX

O

UT

CONTROL

CU

R

RE

NT

SETTING 2

CURRENT

SETTING 1

PRESCALER

V

ALUE

CORE

POWER

LEVEL

OUTPUT

POWER

LEVEL

DB21DB22DB23

POWER-

DOWN 2

POWER-

DOWN 1

COUNTER

RESET

MUTE-TILL-

LD

CP GAIN

CP

THREE-

STATE

PHASE

DETECTOR

POLARITY

PD2P1P2

DB20 DB19 DB18 DB17 DB16 DB15 DB14

DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6

DB5 DB4 DB3 DB2 DB1 DB0

C2 (0) C1 (1)

R1R2R3R4

R5R7R8R9R10R11R12R13R14ABP1ABP2LDPTMB

BSC1 R6

CONTROL

BI

TS

BAND

SEL

ECT

CLOCK

ANTI-

BA

CKLA

SH

PULSE

WIDTH

14-BIT REFERENCE COUNTER

DB21DB22DB23

LOCK

DETECT

PRECISION

TEST

MODE

BIT

RESERVED

DIVIDE-

BY-2

DIVIDE-BY-

2 SELECT

BSC2RSVRSV

DB20 DB19 DB18 DB17 DB16 DB15

DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7

DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (1) C1 (0)

A1A2A3A4A5B1B2B3B4B5B6B7B8

B9B10B11B12B13 RSV

CONTROL

BI

TS

5-BIT A COUNTER

13-BIT B COUNTER

CONTROL LATCH

N COUNTER LATCH

R COUNTER LATCH

DB21DB22

DB23

CP GAIN

RESERVED

CPGDIV2

DIVSEL

04644-016

Data Sheet ADF4360-0

Rev. D | Page 13 of 24

Table 7. Control Latch

DB20

DB19 DB18

DB17 DB16

DB15

DB14 DB13 DB12 DB11 DB10 DB9 DB8

DB7

DB6

DB5

DB4

DB3 DB2

DB1

DB0

C2 (0) C1 (0)

PC1

PC2

CR

M1

M2PDPCPCPGMTLDPL1

PL2CPI1

CPI2

CPI3

CPI4

CPI5

CPI6

PD1 M3

C

ON

T

RO

L

BITS

M

U

X

O

U

T

CO

NT

R

OL

C

UR

RE

N

T

SETTING 2

C

UR

R

EN

T

SETTING 1

P

R

E

S

C

A

L

E

R

V

AL

UE

CORE

POWER

LEVEL

OUTPUT

POWER

LEVEL

DB21

DB22

DB23

POWER-

DOWN 2

POWER-

DOWN 1

COUNTER

RESET

MUTE-TILL-

LD

CP GAIN

CP

THREE-

STATE

PHASE

DETECTOR

POLARITY

PD2P1P2

CR

0

1

COUNTER

OPERATION

NORMAL

R, A, B COUNTERS

HELD IN RESET

PC2

0

1 0

C

OR

E

PO

WE

R

LE

VE

L

5mA

10

m

A

15mA

PC1

0

1

2

0m

A

CP

0

1

CHARGE PUMP

OUTPUT

NORMAL

THREE-STATE

PDP

0

1

PHASE DETECTOR

POLARITY

NE

GA

T

IV

E

POSITIVE

CPG

0

1

CP GAIN

CU

R

RE

NT

S

ET

TI

N

G 1

CU

RRE

NT SE

TTING

2

MTLD

0

1

MUTE-TILL-LOCK DETECT

DI

SABL

ED

E

N

AB

L

ED

M3

M2 M1

O

UT

PU

T

THREE-STATE OUTPUT

0 0 0

0 0

1

0 1 0

0

1 1

1 0 0

1

0 1

1 1 0

1

1 1

DIGITAL LOCK DETECT

(ACTIVE HIGH)

N DIVIDER OUTPUT

DV

DD

R DIVIDER OUTPUT

N-CHANNEL OPEN-DRAIN

LOCK DETECT

SERIA

L D

AT

A

OU

TP

U

T

DGND

P2 P1 PRESCALER VALUE

0 0 8/9

0 1 16/17

1 0 32/33

1 1

32/33

CE PIN PD2 PD1 MODE

0 X X ASYNCHRONOUS POWER-DOWN

1 X

0 NORMAL OPERATION

1

0 1 ASYNCHRONOUS POWER-DOWN

1 1 1 SYNCHRONOUS POWER-DOWN

CPI6

CPI5

CPI4

I

CP

(mA)

CPI3

CPI2

CPI1 4.7kΩ

0.31

0.62

0.93

1.25

1.56

1.87

2.18

2.50

0

1

0

1

0

1

0

1

0

1

0

1

0

1

PL2 PL1

OUTPUT POWER LEVEL

CURRENT

POWER INTO 50Ω (USING 50

Ω TO V

VCC

)

–

13dBm

–

11dBm

–

8dBm

–6dBm

0

1

0

1

0

1

3.5mA

5.0mA

7.5mA

11.0mA

04644-017

ADF4360-0 Data Sheet

Rev. D | Page 14 of 24

Table 8. N Counter Latch

DB20 DB19 DB18 DB17

DB16 DB15

DB14 DB13 DB12 DB11

DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (1) C1 (0)

A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12B13 RSV

CONTROL

BITS

5-BIT A COUNTER

13-BIT B COUNTER

DB21DB22DB23

CP GAIN

DIVIDE-BY-

2 SELECT

DIVIDE-

BY-2

RESERVED

CPGDIV2

DIVSEL

THIS BIT IS NOT USED

BY THE DEVICE AND

IS A DON'T CARE BIT.

A5 A4 .......... A2 A1

A COUNTER

DIVIDE RATIO

0 0 .......... 0 0 0

0 0 .......... 0 1 1

0 0 .......... 1 0 2

0 0 .......... 1 1 3

. . .......... . . .

1 1 .......... 0 0 28

1 1 .......... 0 1 29

1 1 .......... 1 0 30

1 1 .......... 1 1 31

F4 (FUNCTION LATCH)

FASTLOCK ENABLE

CP GAIN OPERATION

CHARGE PUMP CURRENT SETTING 1

IS PERMANENTLY USED

00

CHARGE PUMP CURRENT SETTING 2

IS PERMANENTLY USED

10

N = BP + A; P IS PRESCALER VALUE SET IN THE CONTROL LATCH.

B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY

ADJACENT VALUES OF (N × F

REF

), AT THE OUTPUT, N

MIN

IS (P

2

–P).

B13 B12 B11 B3 B2 B1 B COUNTER DIVIDE RATIO

.......... 00 0 0

0 0 0

0 0 NOT ALLOWED

.......... 0 0 1 NOT ALLOWED

.......... 0 1 0 NOT ALLOWED

.......... 1 1 1 3

.......... .. . .

. . .

.......... . . . .

.......... 11 1 1

1 1 1

0 0 8188

.......... 1 0 1 8189

.......... 1 1 0 8190

.......... 1 1 1 8191

04644-018

DIV2

0

1

DIVIDE-BY-2

FUNDAMENTAL OUTPUT

DIVIDE-BY-2

DIVSEL

0

1

DIVIDE-BY-2 SELECT (PRESCALER INPUT)

FUNDAMENTAL OUTPUT SELECTED

DIVIDE-BY-2 SELECTED

ADF4360-0BCPZRL

ADF4360-0BCPZRL

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