Data Sheet ADF4360-0
Rev. D | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CPGND
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
AV
DD
AGND
RF
OUT
A
RF
OUT
B
V
VCO
DATA
CLK
REF
IN
DGND
C
N
R
SET
V
TUNE
AGND
AGND
AGND
AGND
C
C
CP
CE
AGND
DV
DD
MUXOUT
LE
04644-003
2
1
3
4
5
6
18
17
16
15
14
13
8
9
10
1
1
7
12
20
19
21
22
23
24
ADF4360-0
TOP VIEW
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
2 AV
DD
Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane should be
placed as close as possible to this pin. AV
DD
must have the same value as DV
DD
.
3, 8 to 11, 22 AGND Analog Ground. This is the ground return path of the prescaler and VCO.
OUT
VCO Output. The output level is programmable from −6.5 dBm to −13 dBm. See the Output Matching section for a
description of the various output stages.
5 RF
OUT
B VCO Complementary Output. The output level is programmable from −6.5 dBm to −13 dBm. See the Output
Matching section for a description of the various output stages.
6 V
VCO
Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane should
be placed as close as possible to this pin. V
VCO
must have the same value as AV
DD
.
7 V
TUNE
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP output
voltage.
12 C
C
Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor.
13 R
SET
Connecting a resistor between this pin and CP
GND
sets the maximum charge pump output current for the synthesizer.
The nominal voltage potential at the R
SET
pin is 0.6 V. The relationship between I
CP
and R
SET
is
where R
SET
= 4.7 kΩ, I
CPmax
= 2.5 mA.
14 C
N
Internal Compensation Node. This pin must be decoupled to V
VCO
with a 10 µF capacitor.
16 REF
IN
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and a dc equivalent input resistance of 100
kΩ. See Figure 10. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.
17 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit
shift register on the CLK rising edge. This input is a high impedance CMOS input.
18 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high
impedance CMOS input.
19 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four
latches, and the relevant latch is selected using the control bits.
20 MUXOUT This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be accessed
externally.
21 DV
DD
Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane should be
placed as close as possible to this pin. DV
DD
must have the same value as AV
DD
.
23 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.
Taking the pin high powers up the device depending on the status of the power-down bits.
24 CP Charge Pump Output. When enabled, this provides ± I
CP
to the external loop filter, which in turn, drives the internal VCO.
0 EP Exposed Pad. The exposed pad must be connected to AGND.
