Data Sheet ADF4360-0
Rev. D | Page 17 of 24
Hardware Power-Up/Power-Down
If the ADF4360-0 is powered down via the hardware (using the
CE pin) and powered up again without any change to the N
counter register during power-down, it locks at the correct
frequency because the device is already in the correct frequency
band. The lock time depends on the value of capacitance on the
C
N
pin, which is <5 ms for 10 µF capacitance. The smaller
capacitance of 440 nF on this pin enables lock times of <600 µs.
The N counter value cannot be changed while it is in power-
down because the device may not lock to the correct frequency
on power-up. If it is updated, the correct programming sequence
for it after power-up is to the R counter latch, followed by the
control latch, and finally the N counter latch, with the required
interval between the control latch and N counter latch, as
described in the Initial Power-Up section.
Software Power-Up/Power-Down
If the ADF4360-0 is powered down via the software (using the
control latch) and powered up again without any change to the
N counter latch during power-down, it locks at the correct
frequency because it is already in the correct frequency band.
The lock time depends on the value of capacitance on the C
N
pin, which is <5 ms for 10 µF capacitance. The smaller capacitance
of 440 nF on this pin enables lock times of <600 µs.
The N counter value cannot be changed while it is in power-
down because the device may not lock to the correct frequency
on power-up. If it is updated, the correct programming sequence
for it after power-up is to the R counter latch, followed by the
control latch, and finally the N counter latch, with the required
interval between the control latch and N counter latch, as
described in the Initial Power-Up section.
